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| 20080205343 | Method And System For Allocating SFID In A Worldwide Interoperability Microwave Access Network - A method for allocating an SFID in a WiMAX network including an ASN and a CSN may include: establishing, by the CSN a service flow in response to a service flow creation request from an MSS, and sending the service flow to the ASN; and allocating, by the ASN, a value that currently is not used by the MSS as an SFID of the service flow requested by the MSS. A system for allocating an SFID in a WiMAX network is also provided. According to the method and system for allocating an SFID in a WiMAX network, after an MSS performs a handover, it is not necessary to notify a function module generating an SFID to release the SFID, thereby simplifying the SFID management. | 08-28-2008 |
| 20100056156 | METHOD AND APPARATUS FOR NEGOTIATING SECURITY DURING HANDOVER BETWEEN DIFFERENT RADIO ACCESS TECHNOLOGIES - A method and apparatus of security negotiation for handover between different radio access technologies are provided. The method includes: transmitting the security information of the NAS and AS selected by the target system to the UE when the UE hands over between different radio access technologies. Therefore, the UE can perform security negotiation with the target system according to the security information of the NAS and AS. Through the embodiments of the present invention, the UE may obtain the key parameter information of the NAS and AS selected by the LTE system and perform security negotiation with the LTE system when the UE hands over from a different system, such as a UTRAN, to an LTE system. | 03-04-2010 |
| 20110023094 | METHOD, APPARATUS, AND SYSTEM FOR PREVENTING ABUSE OF AUTHENTICATION VECTOR - A method for preventing abuse of an Authentication Vector (AV) and a system and apparatus for implementing the method are provided. Access network information of a non-3rd Generation Partnership Project (3GPP) access network where a user resides is bound to an AV of the user, so that when the user accesses an Evolved Packet System (EPS) through the non-3GPP access network, even if an entity in the non-3GPP access network is breached, or an Evolved Packet Data Gateway (ePDG) connected to an untrusted non-3GPP access network is breached, the stolen AV cannot be applied to other non-3GPP access networks by an attacker. | 01-27-2011 |
| 20110044455 | Method, Apparatus and System for Key Derivation - A method, an apparatus and a system for key derivation are disclosed. The method includes the following steps: a target base station) receives multiple keys derived by a source base station, where the keys correspond to cells under control of the target base station; the target base station selects a key corresponding to the target cell after knowing a target cell that a user equipment (UE) wants to access. An apparatus for key derivation and a communications system are also provided. | 02-24-2011 |
| 20110165870 | Method, Apparatus and System for Key Derivation - A method, an apparatus and a system for key derivation are disclosed. The method includes the following steps: a target base station) receives multiple keys derived by a source base station, where the keys correspond to cells under control of the target base station; the target base station selects a key corresponding to the target cell after knowing a target cell that a user equipment (UE) wants to access. An apparatus for key derivation and a communications system are also provided. | 07-07-2011 |
| 20110287773 | Method, Apparatus and System for Key Derivation - A method, an apparatus and a system for key derivation are disclosed. The method includes the following steps: a target base station) receives multiple keys derived by a source base station, where the keys correspond to cells under control of the target base station; the target base station selects a key corresponding to the target cell after knowing a target cell that a user equipment (UE) wants to access. An apparatus for key derivation and a communications system are also provided. | 11-24-2011 |
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| 20090326211 | Process for concentrating and processing fluid samples - A method of treating a liquid sample having microbiological target species therein to concentrate the species and collect lysate is disclosed. The liquid sample comprises non-target microbiological particles, inorganic particles, and microbiological target species. The liquid is passed through a prefilter medium to allow the target species to pass through as filtrate and retain non-target microbiological products and inorganic particles thereon. The filtrate is contacted with a main filtration medium adapted to retain the target species thereon as retentate. The retentate is lysed to form a lysate containing target material that was enveloped within the microbiological target species. The microbiological species may comprise cell containing or viral material. Target materials comprise intracellular nucleic acids, or in the case of viral sampling, nucleic acids encased within the protein sheath or coating of the virus. | 12-31-2009 |
| 20110032683 | POWER MODULE AND CIRCUIT BOARD ASSEMBLY THEREOF - A power module includes a first bobbin, a primary winding coil, a circuit board assembly and a first magnetic core assembly. The primary winding coil is wound around the first bobbin. The circuit board assembly includes a printed circuit board, a second winding structure, at least one current-sensing element, a rectifier circuit and an electrical connector. The second winding structure has an output terminal. The current-sensing element includes a first conductor. The first conductor is a conductive sheet. A first end of the first conductor is in contact with the output terminal of the second winding structure. A second end of the first conductor is connected to the rectifier circuit. The primary winding coil is aligned with the second winding structure of the circuit board assembly and arranged within the first magnetic core assembly. The primary winding coil and the electrical connector are electrically connected with a system board. | 02-10-2011 |
| 20110038182 | POWER CONVERTER HAVING SYNCHRONOUS RECTIFIER AND CONTROL METHOD OF SYNCHRONOUS RECTIFIER - Disclosed is a power converter including a switching circuit; a transformer having a primary winding connected to the switching circuit and a secondary winding; a main control circuit connected to the switching circuit for outputting a main control signal to manipulate the switching circuit; at least one synchronous rectifier connected to the secondary winding; at least one current transformer connected to the synchronous rectifier for outputting a detecting signal according to a current flowing through the synchronous rectifier; and at least one synchronous rectification control circuit connected to a control terminal of the synchronous rectifier, the current transformer, and a control terminal of the switching circuit for receiving the detecting signal and the main control signal for manipulating the synchronous rectifier. In case that the main control circuit manipulates the switching circuit to turn on, the synchronous rectification control circuit manipulates the synchronous rectifier to turn on, and thereby allowing the synchronous rectification control circuit to manipulate the synchronous rectifier to turn off according to the detecting signal. | 02-17-2011 |
| 20110129843 | METHOD FOR EVALUATING THE VIRULENCE OF PATHOGENIC BIPHASIC BACTERIA - A method for evaluating relative bacterial virulence of a biphasic bacteria in environmental systems includes measuring the concentration of DNA in the bacteria, measuring the concentration of RNA in the bacteria, determining a ratio of the concentration of RNA to the concentration of DNA and correlating the concentration ratio with a level of relative pathogenicity, wherein the bacteria is preferentially | 06-02-2011 |
| 20110199842 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a first N type semiconductor region provided on a buried oxide layer, a P type semiconductor region provided on the first N type semiconductor region, a gate region provided on the P type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode is taken as a storage node. Via a tunneling effect between bands, holes gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, holes are emitted out from the floating body or electrons are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 08-18-2011 |
| 20110221002 | MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF - The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow. | 09-15-2011 |
| 20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 09-29-2011 |
| 20110248354 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, the devices have hybrid material, GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, prevent polysilicon gate depletion and short channel effects. | 10-13-2011 |
| 20110254013 | HYBRID ORIENTATION ACCUMULATION MODE GAA CMOSFET - A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased. | 10-20-2011 |
| 20110254099 | Hybrid material accumulation mode GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
| 20110254100 | HYBRID MATERIAL ACCUMULATION MODE GAA CMOSFET - A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device has high carrier mobility, high device drive current, and maintains the electrical integrity of the device. Meanwhile, polysilicon gate depletion and short channel effects are prevented. | 10-20-2011 |
| 20110254101 | HYBRID MATERIAL INVERSION MODE GAA CMOSFET - A Ge and Si hybrid material inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of n-type Ge and p-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an inversion mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device. | 10-20-2011 |
| 20110254102 | HYBRID ORIENTATION INVERSION MODE GAA CMOSFET - A hybrid orientation inversion mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of n-type Si (110) and p-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an inversion mode, the devices have different orientation channels, the GAA structure with the racetrack-shaped, high-k gate dielectric layer and metal gate, so as to achieve high carrier mobility, and prevent polysilicon gate depletion and short channel effects. | 10-20-2011 |
| 20110291191 | MOS Structure with Suppressed SOI Floating Body Effect and Manufacturing Method thereof - The present invention discloses a MOS structure with suppressed floating body effect including a substrate, a buried insulation layer provided on the substrate, and an active area provided on the buried insulation layer comprising a body region, a first conductive type source region and a first conductive type drain region provided on both sides of the body region respectively and a gate region provide on top of the body region, wherein the active area further comprises a highly doped second conductive type region between the first conductive type source region and the buried insulation layer. For manufacturing this structure, implant ions into a first conductive type source region via a mask having an opening thereon forming a highly doped second conductive type region under the first conductive type source region and above the buried insulation layer. The present invention will not increase chip area and is compatible with conventional CMOS process. | 12-01-2011 |
| 20110292723 | DRAM CELL UTILIZING FLOATING BODY EFFECT AND MANUFACTURING METHOD THEREOF - The present invention discloses a DRAM cell utilizing floating body effect and a manufacturing method thereof. The DRAM cell includes a P type semiconductor region provided on a buried oxide layer, an N type semiconductor region provided on the P type semiconductor region, a gate region provided on the N type semiconductor region, and an electrical isolation region surrounding the P type semiconductor region and the N type semiconductor region. A diode of floating body effect is taken as a storage node. Via a tunneling effect between bands, electrons gather in the floating body, which is defined as a first storage state; via forward bias of PN junction, electrons are emitted out from the floating body or holes are injected into the floating body, which is defined as a second storage state. The present invention provides a highly efficient DRAM cell utilizing floating body effect with high density, which has low power consumption, has simple manufacturing process, and is compatible to the conventional CMOS and conventional logic circuit manufacturing process. | 12-01-2011 |
| 20120009741 | SOI MOS DEVICE HAVING A SOURCE/BODY OHMIC CONTACT AND MANUFACTURING METHOD THEREOF - The present invention discloses a manufacturing method of SOI MOS device having a source/body ohmic contact. The manufacturing method comprises steps of: firstly creating a gate region, then performing high dose source and drain light doping to form the lightly doped N-type source region and lightly doped N-type drain region; forming an insulation spacer surrounding the gate region; performing large tilt heavily-doped P ion implantation in an inclined direction via a mask with an opening at the position of the N type Si source region and implanting P ions into the space between the N type Si source region and the N type drain region to form a heavily-doped P-type region; finally forming a metal layer on the N type Si source region, then allowing the reaction between the metal layer and the remained Si material underneath to form silicide by heat treatment. In the device prepared by the method of the present invention, an ohmic contact is formed between the silicide and the heavily-doped P-type region nearby in order to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof. Besides, the device of the present invention also has following advantages, such as limited chip area, simplified fabricating process and great compatibility with traditional CMOS technology. | 01-12-2012 |
| 20120012931 | SOI MOS DEVICE HAVING BTS STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a SOI MOS device having BTS structure and manufacturing method thereof. The source region of the SOI MOS device comprises: two heavily doped N-type regions, a heavily doped P-type region formed between the two heavily doped N-type regions, a silicide formed above the heavily doped N-type regions and the heavily doped P-type region, and a shallow N-type region which is contact to the silicide; an ohmic contact is formed between the heavily doped P-type region and the silicide thereon to release the holes accumulated in body region of the SOI MOS device and eliminate floating body effects thereof without increasing the chip area and also overcome the disadvantages such as decreased effective channel width of the devices in the BTS structure of the prior art. The manufacturing method comprises steps of: forming a heavily doped P-type region via ion implantation, forming a metal layer above the source region and forming a silicide via the heat treatment between the metal layer and the Si underneath. The device in the present invention could be fabricated via simplified fabricating process with great compatibility with traditional CMOS technology. | 01-19-2012 |
| 20120018809 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 01-26-2012 |
| 20120021571 | Method of Reducing Floating Body Effect of SOI MOS Device Via a Large Tilt Ion Implantation - The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process. | 01-26-2012 |
| 20120025267 | MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS - A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided. | 02-02-2012 |
