| Patent application number | Description | Published |
| 20090203914 | PROCESS FOR THE PREPARATION OF SOLIFENACIN - A process for the preparation of (1S)-QR)-I -azabicyclo[2.2.2.]oct-3-yl 3,4-dihydro-1-phenyl- 2(1H)-isoquino-line carboxylate by reacting (1S)-alkyl 1-phenyl-1,2,3,4-tetrahydro-2-isoquinoline carboxylate with 3-(R)-quinuclidol in an inert solvent, where a primary alkyl ester of the carboxylate whose alkyl length is C | 08-13-2009 |
| 20100087661 | METHOD FOR THE PREPARATION OF 5-BENZYLOXY-2-(4-BENZYLOXPHENYL)-3-METHYL-1H-INDOLE - A method for the preparation of 5-benzyloxy-2-(4-benzyloxyphenyl)-3-methyl-1H-indole of formula (1) by reaction of 2-bromo-4′-benzyloxypropiophenone and 4-benzyloxyaniline hydrochloride, in which high purity of the product is achieved by isolation of the intermediate, N-(4-benzyloxyphenyl)-α-amino-4-benzyloxypropiophenone of formula (10), in the solid state. The method may be used for the preparation of bazedoxifen of formula (2). | 04-08-2010 |
| 20100240888 | SALTS OF BAZEDOXIFENE - The invention deals with new crystalline salts of bazedoxifene, by means of which a high API quality can be achieved in a high yield. | 09-23-2010 |
| 20110082299 | METHOD FOR THE PREPARATION OF DABIGATRAN - A method for the manufacture of dabigatran of formula VIII, in which the product of a reaction of 4-ethylamino-3-nitrobenzoic acid chloride with ethyl-3-(pyridin-2-ylamino)propanoate, is converted to the hydrochloride using a hydrogen chloride solution producing the compound of formula III-HCl, in which the nitro group is reduced by means of a reaction with sodium dithionite, and the resulting compound of formula IV is subjected to a reaction with [(4-cyanophenyl)amino] acetic acid and oxalic acid, the product of this reaction VI-oxal is then subjected to hydrolysis and a reaction with ammonium carbonate to produce the intermediate of formula VII-HCl, which is then converted to dabigatran by means of a reaction with hexyl chloroformate. | 04-07-2011 |
| Patent application number | Description | Published |
| 20090089729 | Distorted Waveform Propagation and Crosstalk Delay Analysis Using Multiple Cell Models - A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model. | 04-02-2009 |
| 20100005429 | INTEGRATED SINGLE SPICE DECK SENSITIZATION FOR GATE LEVEL TOOLS - One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit. | 01-07-2010 |
| 20100281444 | MULTIPLE-POWER-DOMAIN STATIC TIMING ANALYSIS - Embodiments of a computer system, a method, an integrated circuit and a computer-program product (i.e., software) for use with the computer system are described. These devices and techniques may be used to perform STA for circuits that include multiple power domains. Power-domain crossing information and optionally the delay in each power domain can be propagated during the full circuit graph-based STA to accurately perform STA without enumerating all paths. Some embodiments can use a tag-based engine to track power-domain crossing(s) during graph-based STA. If a power-domain is crossed in a path, pessimism may be added to the cumulative delay at the end point of the path. For those paths that do not cross a power domain, pessimism may be removed from the cumulative delay at their end points. In some embodiments, pessimism may be removed from the cumulative delay at end points for paths that cross power domains. | 11-04-2010 |