| Patent application number | Description | Published |
|---|
| 20090054231 | METHOD FOR PREPARING NANOSTRUCTURED VANADIA-TITANIA CATALYSTS USEFUL FOR DEGRADING CHLORINATED ORGANIC COMPOUNDS BY A FLAME SPRAY PROCESS - The present invention discloses methods for preparing vanadia-titania catalysts in the form of nanostructured particles, where vanadia particles are dispersed at the surface of a titanium dioxide carrier and attached thereto, which are useful for degrading chlorinated organic compounds. The method of the present invention has a number of advantages in that: (i) it is capable of producing vanadia-titania catalysts by a relatively simple process as compared to the conventional wet-type method; (ii) the size of the catalyst particles can be easily regulated; and (iii) the vanadia-titania catalysts prepared according to the method of the present invention exhibit excellent degradation efficiency with respect to chlorinated organic compounds even at a low temperature, compared to catalysts prepared by the wet-type method, due to their nanostructure that provides the catalysts with large reactive surface area and high physical stability. | 02-26-2009 |
| 20090097332 | Semiconductor memory device - A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, generate a source line voltage of which the level is adaptively varied according to a temperature, and a sense amplifier configured to sense a difference in current flowing through the bit lines in response to data read from a selected memory cell, amplify the difference to a level having high output driving capability and output the amplified current. | 04-16-2009 |
| 20090300515 | Web server for supporting collaborative animation production service and method thereof - A web server for supporting a collaborative animation production service. The web server includes a user interface (UI) unit to provide a UI to receive direction data for each scene required for animation production in parallel to users connected to the web server, and a generating unit to combine the direction data input to the UI for each scene and generate an animation corresponding to the combined direction data. A plurality of users thereby collaborate to produce an animation in real time, making it possible to shorten the production time of the animation and produce a high quality animation. | 12-03-2009 |
| 20090302897 | Driver circuit having high reliability and performance and semiconductor memory device including the same - Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node. | 12-10-2009 |
| 20100091913 | APPARATUS AND METHOD FOR ESTIMATING PHASE ERROR BASED ON VARIABLE STEP SIZE - Disclosed is a phase error estimating an apparatus and a method which provides improved convergence speed and tracking speed even in mobile channel environment by variably applying the step size for phase error estimation according to channel status. The apparatus for estimating a phase error includes: a posterior probability (APP) average calculating unit for calculating an APP average value from a soft decision result of a currently received symbol; a step size determining unit for determining a step size variably according to channel status; and a phase error estimating unit for estimating a phase error of the currently received symbol from a phase error of a previously received symbol and the APP average value by using the variably determined step size. | 04-15-2010 |
| 20100118034 | APPARATUS AND METHOD OF AUTHORING ANIMATION THROUGH STORYBOARD - An animation authoring apparatus and method of authoring an animation including a storyboard editor to provide a storyboard editing screen, to interact with a user to edit a storyboard, and to store the edited storyboard, a parser to parse syntax of the edited storyboard, and a rendering engine to convert the edited storyboard into a graphic animation based on the parsed syntax of the edited storyboard. | 05-13-2010 |
| 20100118631 | Semiconductor memory devices with mismatch cells - A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily. | 05-13-2010 |
| 20100124135 | Semiconductor memory devices having hierarchical bit-line structures - The semiconductor memory device includes a memory cell array and a switching circuit. The memory cell array includes a plurality of first memory cells connected between word lines and first local bit lines, and a plurality of second memory cells connected between the word lines and second local bit lines. The switching circuit is configured to respectively connect the first local bit lines to first global bit lines during a first sensing period, and to respectively connect the second local bit lines to second global bit lines during a second sensing period of a reading operation. The semiconductor memory device further includes a sensing circuit configured to sense and amplify data from the first global bit lines during the first sensing period, and to sense and amplify data from the second global bit lines during the second sensing period of the reading operation. | 05-20-2010 |
| 20110013464 | Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device - The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line. | 01-20-2011 |
| 20110029891 | MOBILE TERMINAL AND METHOD OF CONTROLLING OPERATION OF THE MOBILE TERMINAL - A mobile terminal and an operating method of the mobile terminal are provided. The mobile terminal may be coupled, either wirelessly or by wire, to an external terminal and the mobile terminal may thus receive sync data including information regarding a webpage currently being displayed by the external terminal from the external terminal or a server. The mobile terminal may display the same webpage as is currently being displayed by the external terminal based on the received sync data. | 02-03-2011 |
| 20110069569 | SEMICONDUCTOR MEMORY DEVICE COMPRISING TRANSISTOR HAVING VERTICAL CHANNEL STRUCTURE - A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line. | 03-24-2011 |
