| Patent application number | Description | Published |
|---|
| 20090168518 | CHIP SELECT CONTROLLER AND NON-VOLATILE MEMORY DEVICE INCLUDING THE SAME - A chip select controller for a non-volatile memory device includes a first chip enable signal transfer unit, a second chip enable signal transfer unit, a first chip select pad, a second chip select pad, a third chip select pad and a chip select unit. The first chip enable signal transfer unit buffers first and second chip enable signals according to a control signal. The second chip enable signal transfer unit buffers third and fourth chip enable signals according to the control signal. The first chip select pad is configured to transfer a first chip select signal. The second chip select pad is configured to transfer a second chip select signal. The third chip select pad is configured to transfer the second chip select signal. The chip select unit addresses a specific chip according to the first chip select signal and the second chip select signal. | 07-02-2009 |
| 20090185419 | PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME - A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation. | 07-23-2009 |
| 20090185420 | PAGE BUFFER CIRCUIT WITH REDUCED SIZE AND METHODS FOR READING AND PROGRAMMING DATA WITH THE SAME - A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation. | 07-23-2009 |
| 20090196099 | PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD - A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data. | 08-06-2009 |
| 20090196111 | PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD - A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data. | 08-06-2009 |
| 20090207669 | PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD - A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data. | 08-20-2009 |
| 20090287972 | TEST METHOD FOR NONVOLATILE MEMORY DEVICE - A test method for nonvolatile memory devices where, in one aspect of the method, a specific operation mode is selected according to a signal input through a single I/O pin in a period in which a write enable signal is inactivated. The write enable signal or a read enable signal is activated according to the selected operation mode. A plurality of signals is input through the single I/O pin in a period in which the write enable signal is activated. The plurality of signals is output through the single I/O pin in a period in which the read enable signal is activated. | 11-19-2009 |
| 20090290435 | NONVOLATILE MEMORY DEVICE AND METHOD OF TESTING THE SAME - A nonvolatile memory device includes a clock input stage configured to receive a clock signal for a test, a control signal output unit configured to output data input-output (IO) control signals according to the clock signal, n number of IO stages for data IO, and n number of storage units connected to the respective n number of IO stages and configured to temporarily store data to be exchanged between the respective n number of IO stages and internal circuits according to the respective data IO control signals. The n number of storage units are further commonly connected to a first IO stage of the n number of IO stages and configured to sequentially input or output data through the first IO stage in a test mode according to the respective data IO control signals. | 11-26-2009 |
| 20100329042 | MEMORY CHIP PACKAGE WITH EFFICIENT DATA I/O CONTROL - A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit. | 12-30-2010 |
| 20110075479 | MULTI-LEVEL CELL COPYBACK PROGRAM METHOD IN A NON-VOLATILE MEMORY DEVICE - A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation. | 03-31-2011 |
