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| 20090147499 | Light diffusion film with uniform surface roughness and low retardation value, display including the same, and associated methods - A light diffusion film includes a thermoplastic resin, a surface of the light diffusion film has a roughness (Ra) of about 0.5 to about 3 μm and a height distribution index (HDI) of about 3 to about 8 μm, and the light diffusion film has a retardation of not more than about 25 nm. | 06-11-2009 |
| 20100149648 | Method of extrusion molding prism film and prism film manufactured by the same - A method of extrusion molding a prism film and a prism film manufactured by the same, the method including providing a molten film, simultaneously forming a prism pattern and an embossed pattern on opposite surfaces of the molten film by passing the molten film through a gap between a prism roll and an emboss roll, and cooling the molten film having the prism pattern and the embossed pattern on opposite surfaces thereof. | 06-17-2010 |
| 20100151204 | Light diffusion film and method for manufacturing the same - A light diffusion film includes a thermoplastic resin, wherein a surface of the light diffusion film has an embossed pattern thereon, and the surface of the light diffusion film having the embossed pattern has a surface roughness (Ra) of about 0.5 μm to about 3 μm and a height distribution index (HDI) of about 3 μm to about 8 μm. | 06-17-2010 |
| 20110116014 | OPTICAL LAMINATE FILM, BACKLIGHT UNIT INCLUDING THE SAME, AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME - An optical laminate film, a backlight unit, and a liquid crystal display module, the optical laminate film including a multilayer film composed of multiple layers including at least two polymers having different refractive indexes, the multilayer film transmitting only a light component vibrating in a direction parallel to one transmittance axis while reflecting other light components; an embossed diffusing film laminated on one side of the multilayer film, the embossed diffusing film having roughness on a surface thereof; and a microlens film laminated on another side of the multilayer film, the microlens film having microlenses arranged on a surface thereof. | 05-19-2011 |
| 20110164321 | DIFFUSING FILM HAVING MICRO LENS PATTERN AND EMBOSSED PATTERN - A diffusing film may have a microlens pattern and an embossed pattern on the surface thereof. The diffusing film includes a light entrance plane for receiving incident light, a light exit plane opposite the light entrance plane, the light exit plane for transmitting light, a plurality of microlenses on a surface of the light exit plane of the diffusing film, microlenses of the plurality of microlenses being spaced apart from one another, and a separation plane between the plurality of microlenses, the separation plane having an embossed pattern on a surface thereof. | 07-07-2011 |
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| 20090197329 | APPARATUS AND METHOD FOR SEPARATING BIOLOGICAL PARTICLES USING DIFFERENCE BETWEEN GRAVITY AND MAGNETIC FORCE - Disclosed is an apparatus and method for injecting liquid-drops of particle mixture liquid including a mixture of biological particles, affecting magnetic field, and having only positive particles, which are combined with magnetic responsive material, separated by magnetic force, and having negative particles, which are not combined with magnetic responsive material, precipitated by gravity. | 08-06-2009 |
| 20090267702 | PRINTED CIRCUIT BOARD FOR DECREASING WIRELESS WIDE AREA NETWORK NOISE - A printed circuit board (PCB) capable of decreasing wireless wide area network (WWAN) noise generated due to internal signal interference occurring in the PCB is disclosed. The PCB printed circuit board includes a first layer, a second layer, and at least one insulating layer formed between the first and second layers. The PCB board further includes a first signal line group disposed on the first layer while including a plurality of first signal lines each supplying a first signal, isolation patterns disposed on the first layer such that the isolation patterns are arranged between adjacent ones of the first signal lines, respectively, to prevent the adjacent first signal lines from interfering with each other, and a second signal line group disposed on the second layer while including a plurality of second signal lines each supplying a second signal different from the first signal. The second signal line group corresponds to the isolation patterns. | 10-29-2009 |
| 20090267706 | RESONATOR AND FABRICATION METHOD THEREOF - A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level. | 10-29-2009 |
| 20110039032 | Method of manufacturing polymer dispersed liquid crystal display device including dichroic dye - Example embodiments relate to a method of manufacturing a polymer dispersed liquid crystal (PDLC) display device including dichroic dye. The method may include filling a mixture solution including liquid crystals, a photopolymerizable material, dichroic dyes, and liquid crystalline polymers in a space between a first electrode and a second electrode that face each other; applying an electric field between the first electrode and the second electrode; and arranging the dichroic dyes in the mixture solution. | 02-17-2011 |
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| 20090127609 | Method of fabricating recess channel transistor having locally thick dielectrics and related devices - Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate. | 05-21-2009 |
| 20090152625 | Recessed channel transistor - A recessed channel transistor includes a single crystalline silicon substrate having a recessed portion, a bottom surface of the recessed portion including an elevated central portion, a channel doping region in the single crystalline silicon substrate, the channel doping region being under the bottom surface of the recessed portion, a gate structure in the recessed portion, and source/drain regions in the single crystalline silicon substrate at both sides of the recessed portion, the source/drain regions being spaced apart from the bottom surface of the recessed portion. | 06-18-2009 |
| 20090176342 | Method of fabricating semiconductor device having deifferential gate dielectric layer and related device - A semiconductor device and method of fabricating a semiconductor device are provided. The method includes forming a gate trench in a semiconductor substrate to define source/drain regions. The source/drain regions are separated from each other by the gate trench, and the semiconductor substrate is exposed through the gate trench. The semiconductor substrate has impurities of a first conductivity type. The source/drain regions have impurities of a second conductivity type different from the first conductivity type. The concentration of the second conductivity type impurities increases as the impurities approach the surfaces of the source/drain regions. A differential gate dielectric layer is formed along the surfaces of the source/drain regions and the semiconductor substrate exposed through the gate trench. A gate electrode filling the gate trench is formed. The differential gate dielectric layer has a first thickness between the gate electrode and the semiconductor substrate and has a second thickness greater than the first thickness between the gate electrode: and the source/drain regions. | 07-09-2009 |
| 20100237408 | Recessed channel transistor - A recessed channel transistor includes an isolation layer provided in a semiconductor substrate to define an active region. A trench is provided in the semiconductor substrate to extend across the active region. A gate insulation layer covers a sidewall and a bottom face of the trench and an upper face of the semiconductor substrate adjacent to an upper edge of the trench, wherein a portion of the gate insulation layer on the upper surface of the semiconductor substrate adjacent to the upper edge of the trench and on the sidewall of the trench extending to a first distance downwardly from the upper edge of the trench has a thickness greater than that of a portion of the gate insulation layer on the remaining sidewall and the bottom face of the trench. A gate electrode fills up the trench having the gate insulation layer formed therein. | 09-23-2010 |
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| 20080296670 | Semiconductor Devices Including Transistors Having a Recessed Channel Region and Methods of Fabricating the Same - Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein. | 12-04-2008 |
| 20090114967 | TRANSISTORS HAVING A CHANNEL REGION BETWEEN CHANNEL-PORTION HOLES AND METHODS OF FORMING THE SAME - According to some embodiments of the invention, transistors have channel regions between channel-portion holes. Methods of forming the same include at least two channel-portion holes disposed in a semiconductor substrate. Line patterns are formed in parallel to be spaced apart from each other on a main surface of the semiconductor substrate to fill the channel-portion holes. A channel region is disposed in the semiconductor substrate below the line patterns. At this time, the channel region is formed between the channel-portion holes and also covers lower portions of the channel-portion holes. Driving current capability and refresh characteristics of DRAMs utilizing the inventive transistors are improved. | 05-07-2009 |
| 20090191683 | METHOD OF FORMING TRANSISTOR HAVING CHANNEL REGION AT SIDEWALL OF CHANNEL PORTION HOLE - According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern. | 07-30-2009 |
| 20100102385 | Semiconductor Devices Including Transistors Having Recessed Channels - Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein. | 04-29-2010 |
| 20100170791 | BIOSENSOR AND READOUT METER - The present invention relates to a biosensor for selectively performing quantitative analysis on a specific substance contained in a biological sample and a readout meter using the same. The inventive biosensor comprises an electrode for recording identification information of the biosensor thereon. The electrode has an electrode pattern and a plurality of contact points formed thereon according to the identification information, and the identification information is recorded on the electrode based on the ratio of resistances between the plurality of contact points. According to the present invention, various items of identification information such as in | 07-08-2010 |
