Patent application number | Description | Published |
20090085605 | SYSTEM AND METHOD FOR PARALLEL BURNING USING MULTIPLEX TECHNOLOGY - A system and method for parallel burning using multiplex technology is used for burning chips of different bus types on the same transmission bus at the same time in parallel. A main control unit divides bandwidth of the transmission bus into different frequency bands, sends a control command including a command for sending data carrying bus signals of designated types, and controls data carrying the bus signals of the designated types to be transmitted in designated frequency bands of the transmission bus. Then, a sending unit sends the data carrying the bus signals of the designated types in the designated frequency band. Finally, receiving units receive the data transmitted in the designated frequency bands, and then output them to a plurality of burners such as to burn the data onto the chips of the designated bus types in parallel. | 04-02-2009 |
20090089003 | Accessory-testing device and method therefor - An accessory-testing device for an information processing apparatus includes a micro-processing unit (MPU) and a signal conversion unit. The MPU sends a mimic signal. The signal conversion unit is electrically connected to the MPU and an accessory respectively, for receiving the mimic signal and converting the mimic signal into a test signal to test the accessory. The accessory receives the test signal and then responds to the test signal to output a feedback signal. The feedback signal is received by the signal conversion unit and transmitted to the MPU, such that the MPU determines if the accessory operates normally according to the feedback signal. Conventional testing methods are Therefore, it is achieved that the effects of reducing the inspection time and improving the production efficiency. | 04-02-2009 |
20090089469 | Parallel burunig system and method - A parallel burning system and method is for burning chips of various different bus types in parallel. A computer compiles configuration information according to corresponding connection relations between the chips and the micro controller units, and transmits the configuration information, burning command and burning data to a master micro controller unit of the micro controller units. The master micro controller unit distributes the burning data to slave micro controller units of the micro controller units based on the analyzed configuration information, and controls each slave micro controller unit to activate its burning operation. Then, the slave micro controller units burn the burning data onto the chips connected thereto, and transmit the burning results back to the master micro controller unit after completion of the burning operations. Finally, the master micro controller unit transmits the burning results back to the computer after completion of all the burning operations. | 04-02-2009 |
20090113454 | SYSTEM AND METHOD OF TESTING BRIDGE SAS CHANNELS - A system and a method of testing bridge SAS channels includes a control terminal, a hot-plug bridge interface, a first adaptor, an SAS back plate, and a second adaptor. The control terminal selects an SAS interface as a transmission path for sending a test signal. The hot-plug bridge interface receives and converts the test signal sent from the control terminal. The hot-plug bridge interface has a hot-plug function. The first adaptor is connected to the hot-plug bridge interface and the SAS back plate. The second adaptor is connected between the SAS back plate and a terminal unit. The control terminal sends the test signal and detects a signal under test sent back from the terminal unit, and compares whether they are consistent with each other or not. In this way, the control terminal determines whether the SAS interfaces in the SAS back plate run normally or not. | 04-30-2009 |
Patent application number | Description | Published |
20120092121 | BALANCED TRANSFORMER STRUCTURE - A multi-chip electronic device includes a first winding having a first port (P+) and a second port (P−). The first winding is formed in a metal layer of a first chip. The device further includes a second winding having a third (S+) and a fourth port (S−). The second winding is formed in a metal layer of a second chip. A center tap of the second winding is connected to a reference potential. | 04-19-2012 |
20120122395 | THROUGH CHIP COUPLING FOR SIGNAL TRANSPORT - Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit. | 05-17-2012 |
20130038418 | CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL - A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils. | 02-14-2013 |
20130106532 | BAND-PASS FILTER USING LC RESONATORS | 05-02-2013 |
20130181534 | THROUGH-CHIP INTERFACE (TCI) STRUCTURE FOR WIRELESS CHIP-TO-CHIP COMMUNICATION - A transformer for RF and other frequency through-chip-interface (TCI) applications includes multiple chips in wireless electronic communication with one another in three-dimensional integrated circuit, 3DIC, technology. Each of the chips includes an inductor coil and a matching network that matches the impedance of the inductor coil. The matching network is electrically coupled between the inductor coil and further components and circuits formed on the chip. | 07-18-2013 |
20130207230 | ON-CHIP FERRITE BEAD INDUCTOR - A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes. | 08-15-2013 |
20130328623 | LOW POWER ACTIVE FILTER - Some embodiments relate to a band-pass filter arranged in a ladder-like structure. The band-pass filter includes respective inductor-capacitor (LC) resonators arranged on respective rungs of the ladder-like structure. Respective matching circuits are arranged on a leg of the ladder-like structure between neighboring rungs. | 12-12-2013 |
20140036396 | INTEGRATED PASSIVE DEVICE FILTER WITH FULLY ON-CHIP ESD PROTECTION - The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology. | 02-06-2014 |
20140132333 | SWITCH CIRCUIT AND METHOD OF OPERATING THE SWITCH CIRCUIT - A method of electrically coupling a first node and a second node of a switch cell includes biasing the second node and a bias node of the switch cell at a direct current (DC) voltage level of a second voltage level greater than a first voltage level. A first switch unit coupled between the first node and the second node is tuned on by a first control signal having a third voltage level. The third voltage level being greater than the first voltage level, and a difference between the third voltage level and the first voltage level is about twice a difference between the second voltage level and the first voltage level. Also, a second switch unit coupled between the second node and the bias node is turned off by a second control signal having the first voltage level. | 05-15-2014 |
20140184275 | POWER CELL, POWER CELL CIRCUIT FOR A POWER AMPLIFIER AND A METHOD OF MAKING AND USING A POWER CELL - A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer. | 07-03-2014 |
20140256063 | CONTACTLESS COMMUNICATIONS USING FERROMAGNETIC MATERIAL - A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils. | 09-11-2014 |
20140266419 | VOLTAGE CONTROLLER FOR RADIO-FREQUENCY SWITCH - One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. | 09-18-2014 |
20140266512 | CMOS BAND-PASS FILTER - A band-pass filter is provided that is configured to output a signal with a frequency within a desired frequency range and to attenuate signals with frequencies outside the desired frequency range. The band-pass filter comprises a CMOS resonator that comprises a resonator cavity and a reflector. The band-pass filter also comprises an impedance convertor that is configured to inhibit at least some insertion losses on the band-pass filter. The band-pass filter also comprises a variable capacitor that is connected between the CMOS resonator and the impedance convertor. The desired frequency range of the band-pass filter can be tuned by adjusting the capacitance of the variable capacitor. | 09-18-2014 |
20150014786 | HIGH PERFORMANCE POWER CELL FOR RF POWER AMPLIFIER - A power cell designed for an RF power amplifier comprises an enhancement MOSFET formed in an P-Well in an P-Substrate and a depletion or Schottky MOSFET formed in an N-Well in the same P-Substrate with a horizontal or a vertical channel between the source, drain, and gate electrodes of the depletion or Schottky MOSFET. The source node of the enhancement MOSFET and source node of the depletion or Schottky MOSFET are connected together to form the power cell. | 01-15-2015 |
20150015336 | CMOS CASCODE POWER CELLS - A circuit includes a first CMOS device forming a gain stage of a power amplifier and a second CMOS device forming a voltage buffer stage of the power amplifier. The first CMOS device includes a first doped well formed in a substrate, a first drain region and a first source region spaced laterally from one another in the first doped well, and a first gate structure formed over a first channel region in the first doped well. The second CMOS device includes a second doped well formed in the semiconductor substrate such that the first doped well and the second is disposed adjacent to the second doped well. A second drain region and a second source region are spaced laterally from one another in the second doped well, and a second gate structure formed over a second channel region in the second doped well. | 01-15-2015 |
Patent application number | Description | Published |
20120126630 | SYSTEM AND METHOD FOR INDUCTIVE WIRELESS SIGNALING - A transformer includes first and second semiconductor substrates. The first semiconductor substrate includes a first circuit, a first coil providing a first impedance, and a first capacitor coupled in parallel with the first coil. The second semiconductor substrate includes a second circuit, a second coil providing a second impedance and inductively coupled with the first coil, and a second capacitor coupled in parallel with the second coil. | 05-24-2012 |
20120208457 | CAPACITIVE PROXIMITY COMMUNICATION USING TUNED-INDUCTOR - A multi-chip module includes a chip stack package including at least one pair of stacked dies, the dies having overlapping opposing faces, and at least one capacitive proximity communication (CPC) interconnect between the pair of stacked dies. The CPC interconnect includes a first capacitor plate at a first one of the overlapping opposing faces and a second capacitor plate at a second one of the overlapping opposing faces spaced from and aligned with the first capacitor plate. The CPC interconnect further includes an inductive element connected in series with the first capacitor plate and second capacitor plate, wherein the capacitor plates form part of a capacitor and the capacitor cooperates with the inductor element to form a LC circuit having a resonant frequency. | 08-16-2012 |
20120212865 | ESD BLOCK ISOLATION BY RF CHOKE - A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit. | 08-23-2012 |
20120229318 | DEVICES AND BANDPASS FILTERS THEREIN HAVING AT LEAST THREE TRANSMISSION ZEROES - A bandpass filter comprises a first capacitor, a second capacitor, a third capacitor and at least two resonators. The first and second capacitors are coupled in parallel with each other, and each of the first and second capacitors includes an input. The third capacitor is coupled between the first capacitor and the second capacitor at their respective inputs. The at least two resonators are coupled in parallel with the first capacitor and the second capacitor and are positioned adjacent to each other at a distance such that the at least one component of the resonators are electromagnetically coupled together to provide three (3) transmission zeros. | 09-13-2012 |
Patent application number | Description | Published |
20140374790 | Structure of a Trench MOS Rectifier and Method of Forming the Same - A structure of trench MOS rectifier and a method of forming the same are disclosed including a plurality of trenches formed in the n− drift epitaxial layer, a plurality of MOS structure formed on the substrate either in discrete islands or in rows. Asides the MOS gates there are source regions formed under the mesas. A top metal served as an anode is then formed on the resulted front surface connecting the MOS gates and the adjacent source regions. | 12-25-2014 |
20140374818 | Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same - A structure of trench VDMOS transistor comprises an n− epi-layer/n+ substrate having trench gates formed therein, which have a trench oxide layer conformally formed and filled with a first poly-Si layer. A plurality of MOS structure formed on the mesas. Doubled diffused source regions are formed asides the MOS structure. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer patterned as two is formed on inter-metal dielectric layer. The one is for source regions and the first poly-Si layer connection by source contact plugs and the other for the gate connection by gate contact plugs. In the other embodiment, the trenches are filled with a stack layer of a first oxide layer/a first poly-Si layer. The MOS gates with their second poly-Si layer in a form of rows are formed on the first oxide layer and the mesas. An inter-metal dielectric layer is formed on the resulted surfaces. An interconnecting metal layer is formed on the inter-metal dielectric layer and through the source contact plugs connecting the source regions and the first poly-Si layer. The drain electrode is formed on the rear surface of the n+ substrate for both embodiments. | 12-25-2014 |
20140374820 | DUAL TRENCH MOS TRANSISTOR AND METHOD FOR FORMING THE SAME - A dual trench MOS transistor comprises of the following elements. A plurality of trenches are formed in an n− epitaxial layer on a heavy doped n+ semiconductor substrate and spaced to each other by one mesa. Each the trench has a trench oxide layer formed on a bottom and sidewalls thereof. A first polysilicon layer is formed in the trenches. A plurality of recesses are formed in the mesas and spaced to each other with one sub-mesa. Each the recess has a recess oxide layer formed on a bottom and sidewalls thereof. A second polysilicon layer for serving as a gate is formed in the recesses. The mesas are implanted to have implanted areas at two side of the gate. The implanted areas and the first polysilicon layer are applied to serve as the source. The rear surface of the substrate is served as the drain. | 12-25-2014 |
20150035047 | Dual Trench Rectifier and Method for Forming the Same - A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n− epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode. | 02-05-2015 |
20150287720 | DUAL TRENCH RECTIFIER AND METHOD FOR FORMING THE SAME - A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n− epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode. | 10-08-2015 |
Patent application number | Description | Published |
20080230958 | In-Mould Coating Method and Device for the Same - An in-mould coating method and a coating device for the same, wherein the inserts in the mould of the coating device are made of transparent material and are each coated with reflective material. In each insert are installed light generators, light sensors, cameras, etc. The coating method comprises the steps of: closing the mould after placing a semi-finished product formed by injection molding or other processes in the mould; injecting liquid lacquer or other liquid coating material, and using the cameras to monitor filling; and after finishing filling, starting the light generators and utilizing the light sensors to monitor the amount of light irradiated on the injected liquid lacquer or other liquid coating materials in such a manner that the injected liquid lacquer or other liquid coating materials is hardened to form a coating film on the surface of the semi-finished product. | 09-25-2008 |
20110174218 | IN-MOULD COATING DEVICE - An in-mould coating device comprises a fixed insert, a light generator, a camera, a light sensor, a bolster, a moving insert, the fixed insert is disposed in a fixed plate, the light generator, camera and light sensor are disposed in the fixed insert and equipped with on-off and control wires, the bolster is attached to a bottom of the fixed insert to fix the fixed insert, the camera and light sensor; the fixed inserted is made of transparent material selected from the group consisting of quartz, glass, crystal and coated with a reflective layer on an outer surface thereof, light generated from the light generator is reflected by the reflective layer, photo-curing coating materials are injected into a clearance between the fixed insert and the moving insert and irradiated by the light directly generated from the light generator and multidirectional light reflected by the reflective layer. | 07-21-2011 |
20120043702 | PROCESSING METHOD FOR IN-MOLD COATING INTEGRATIVE SYSTEM - A processing method for in-mold coating integrative system is used in cooperation with an injection molding machine. The injection molding machine comprises a rotatable work platform and a combination of at least one male mold and at least two female molds. The rotatable work platform is divided averagely into several work areas, and the processing proceeds sequentially in each work area by the rotation of the rotatable work platform. The processing method comprises following steps: injection molding a solid workpiece firstly, and leaving the solid work-piece on the male mold; rotating the rotatable work platform; performing surface coloring; rotating the rotatable work platform; injecting UV top-coat, the top-coat female mold is made of light-directing material and has a die cavity and a UV paint cavity on the surface of the solid workpiece, and a UV top-coat layer is injected into the UV paint cavity through a paint channel; irradiating the UV top-coat layer by a UV top-coat hardening lamp; and demolding to achieve a finished product. The method is of benefit to mass production, and can reduce labor cost and processing cost. | 02-23-2012 |
Patent application number | Description | Published |
20130113347 | LOCKING MECHANISM WITH EASY ASSEMBLY AND ELECTRONIC DEVICE THEREWITH - A locking mechanism includes a lock for passing through an opening of a housing. The lock includes a lock head, a cover whereon a slot is formed, a constraining portion, and a platform structure for contacting against a fastening portion of the housing as the cover passes through the opening. The locking mechanism further includes a tongue piece installed on a side of the cover and rotating with the lock head synchronously. The tongue piece includes a latching portion for latching inside an indentation of a door as the tongue piece rotates to a latching position, and a stopping portion for contacting against an end of the constraining portion as the tongue piece rotates to the latching position. The locking mechanism further includes a jump ring for engaging inside the slot on the cover so as to fix the lock inside the housing. | 05-09-2013 |
20140001942 | Latch Mechanism, Electronic Apparatus Having the Same, and Method for Removing a Shell Cover from a Shell Base Using the Same | 01-02-2014 |
20150056039 | INTERNALLY THREADED POST, ASSEMBLING STRUCTURE AND ASSEMBLING METHOD - An internally threaded post adapted to be fixed to a first shell is provided. The first shell has a boss, and the boss has an opening. The internally threaded post includes a screwing portion and a fixing portion. The screwing portion has a threaded hole, in which an outer diameter of the screwing portion is larger than an inner diameter of the opening. The fixing portion is connected with the screwing portion, in which an outer diameter of the fixing portion is smaller than the outer diameter of the screwing portion, and the fixing portion is fixed in the opening. In addition, an assembling structure having the internally threaded post and an assembling method are also provided. | 02-26-2015 |