| Patent application number | Description | Published |
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| 20090212861 | LOW NOISE AMPLIFIER - A low noise amplifier is provided. The low noise amplifier includes: a low noise amplifying unit amplifying an input signal; a harmonic and noise generating unit disposed in an input terminal of the low noise amplifying unit, for generating a compensating signal for compensating for an intermodulation distortion signal and a thermal noise signal of the input signal to the low noise amplifying unit; and a load unit outputting the amplified input signal generated by the low noise amplifying unit. | 08-27-2009 |
| 20090215421 | RF RECEIVER AND METHOD OF RECEIVING RF SIGNAL - A radio frequency (RF) receiver and a method of receiving an RF signal are provided. The RF receiver includes a low-noise amplifying unit which amplifies a received signal while restricting out-of-band interferer of the received signal, a sampling unit which performs sampling to convert the amplified signal to a discrete time domain signal, a frequency translation unit which down-converts the sampled signal into a frequency band that enables the sampled signal to be converted into a digital signal and restricts interferer from a frequency within an aliasing band according to a sampling frequency, an anti-aliasing filtering unit which prevents aliasing from the down-converted signal, a clock unit which provides the sampling unit, the frequency translation unit, and the anti-aliasing filtering unit with sampling frequencies, and an analog-digital-converter which converts the converted signal into the digital signal. | 08-27-2009 |
| 20090327793 | FINITE IMPULSE RESPONSE (FIR) FILTER WITHOUT DECIMATION - Provided is a discrete signal finite impulse response (FIR) filter and a filter set in which a plurality of FIR filter units are connected in a cascade structure to remove down-sampling by decimation, in order to improve the attenuation characteristics of a FIR filter, such as, for example, a switched capacitor filter. The FIR filter includes a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample. Each sub block being in a state among a number of possible states including N charging states for storing the received sample, a transfer state for outputting the stored sample and a reset state for operation initialization. The N charging states, the transfer state and the reset state are changed sequentially in response to the clock signals. | 12-31-2009 |
| Patent application number | Description | Published |
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| 20080309281 | Starting Control Apparatus and Method for Motor - An exciting coil of a motor is formed to be controlled by using an analog timer to thus control an excitation control circuit of a motor control apparatus, whereby an excitation control circuit that excites an exciting coil of a motor control apparatus can be simplified and complexity can be reduced by simplifying a circuit construction of an excitation controller. The present invention includes: an auxiliary winding (sub-coil) and a main winding (main coil); and an exciting unit which is electrically connected with the auxiliary winding and the main winding, determines an excitation application time and an excitation time, and generates an excitation current according to the determined excitation application time and the excitation time. | 12-18-2008 |
| 20090108796 | Starting Control Apparatus and Method for Motor - An apparatus and method for controlling starting of a motor are disclosed. An exciting coil of a motor is excited by using a controller of an electronic refrigerator without having an extra excitation control circuit, to thereby simplify a component construction for controlling exciting of the motor and thus reduce complexity. The present invention includes: a main coil and an auxiliary coil (sub-coil); an exciting coil that generates an excitation current; a refrigerator control unit that outputs a control signal for controlling an application time of the excitation current when started; and a switch unit electrically connected with the exciting coil and supplying power to the exciting coil according to the control signal outputted from the refrigerator control unit. | 04-30-2009 |
| 20090160393 | Starting Control Apparatus and Method for Motor - Entry of a synchronous speed of a rotor can be facilitated by increasing a starting torque by adjusting a magnetization application time for magnetizing the rotor according to whether or not a starting capacitor is used. The present invention includes: a control unit that outputs a control signal for controlling an application time of a magnetizing current according to whether or not a starting capacitor is used; and a switch that supplies power to an exciting coil according to the control signal outputted from the control unit. | 06-25-2009 |
| 20090236925 | Self Magnetizing Motor - A self magnetizing motor, in which a magnetic substance is disposed at the rotor and a stator is provided with a magnetizing portion to magnetize the magnetic substance, and the magnetizing portion forms an exciter pole protruding toward the magnetic substance and a tip portion tapered at an end of the exciter pole, wherein a width of the exciter pole, a protruding length of the tip portion, and a width of the tip portion are formed in the ratio of 8-9:2-2.5:1-2.4, thereby increasing the intensity of magnetizing of the magnetic substance thus to improve the motor performance. | 09-24-2009 |
| Patent application number | Description | Published |
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| 20080204081 | Clock gated circuit - A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power or ground voltage; and an output unit that inverts a logic level of the fighting node to generate the gated clock signal. A blocking unit can be included that blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. A blocking transistor can be included that prevents unnecessary electric charge from inflowing into the fighting node to reduce power consumption and discharging time. | 08-28-2008 |
| 20080284472 | APPARATUS FOR ADJUSTING BANDWIDTH AND CENTRAL FREQUENCY OF OSCILLATING SIGNAL GENERATED FROM CHAOTIC SIGNAL AND METHOD FOR GENERATING SIGNAL THEREOF - A communication apparatus and a method for generating a signal thereof are provided. The communication apparatus adjusts a bandwidth or central frequency of an oscillating signal which is generated from a chaotic signal to be used in the modulation, or adjusts both the bandwidth and the central frequency. Accordingly, it is possible to transform the oscillating signal generated from the chaotic signal more diversely and thus to modulate an information signal more diversely and more adaptively. | 11-20-2008 |
| 20090009400 | MINIATURIZED MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) ANTENNA - A miniaturized multiple input multiple output (MIMO) antenna includes a first antenna element disposed in a first side of a substrate in a round form; a second antenna element in a round form symmetrically with the first antenna element and disposed in the first side of the substrate; and a ground disposed in a second side of the substrate. The first antenna element and the second antenna element are disposed such that electro magnetic waves resonating in the first antenna element and the second antenna element are orthogonally polarized. Accordingly, the antenna size can be reduced. The miniaturized antenna facilitates the component design in the small terminal. | 01-08-2009 |
| 20090201069 | LEVEL SHIFTING CIRCUIT - A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal. | 08-13-2009 |
| 20110231723 | FLIP-FLOP CIRCUIT AND SCAN FLIP-FLOP CIRCUIT - A scan flip-flop circuit includes a pulse generator, a dynamic input unit and a latch output unit. The pulse generator generates a pulse signal which is enabled in synchronization with a rising edge of a clock signal in a normal mode, and is selectively enabled in synchronization with the rising edge of the clock signal in response to a logic level of a scan input signal in a scan mode. The dynamic input unit precharges a first node to a power supply voltage in a first phase of the clock signal, selectively discharges the first node in the normal mode, and discharges the first node in the scan mode. The latch output unit latches an internal signal provided from the first node to provide an output data, and determines whether the output data is toggled based on the clock signal and a previous state of the output data. | 09-22-2011 |
