Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Jin Lu
Jin Lu, Lafayette, CO US
| Patent application number | Description | Published |
|---|---|---|
| 20090019335 | AUXILIARY PATH ITERATIVE DECODING - A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory. | 01-15-2009 |
| 20110029843 | CYCLE SLIP DETECTION AND CORRECTION - A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip. | 02-03-2011 |
| 20110107187 | High Density Tape Drive Multi-Channel Low Density Parity Check Coding Control - An LDPC coding system includes a number of LDPC encoders and a number of LDPC decoders. The number of encoders/decoders is between one and one fewer than the total number of tracks on the high density tape are provided. The LDPC encoders are operable to break data from an incoming data sector into the data blocks to be written to the high density tape. The LDPC decoders are operable to assemble the data blocks into data sectors. | 05-05-2011 |
Jin Lu, Shenzhen City CN
| Patent application number | Description | Published |
|---|---|---|
| 20110091316 | FAN ASSEMBLY WITH SNAP-ON COVER - An exemplary fan assembly includes a fan and a snap-on cover. The fan includes a bracket and an impeller disposed in the bracket. The cover includes a base body, a number of first clasps extending outwardly from a first side of the base body, a number of retaining clasps extending outwardly from an opposite second side of the base body, and an operation portion connecting the retaining clasps. The base body is disposed on the bracket, the first clasps clasp a first side of the bracket, the retaining portions clasp an opposite second side of the bracket, and the operation portion presses the bracket. | 04-21-2011 |
| 20110127006 | HEAT DISSIPATION DEVICE - An exemplary heat dissipation device includes mounting feet and fasteners mounted on the mounting feet. Each fastener includes a shaft and two latching portions extending outwardly from an outer circumference of an end of the shaft. Each mounting foot defines a through hole allowing extension of the end of the shaft with two second portions. Each mounting foot defines two latching recesses in a surface thereof. Each of the latching recesses defines two blocking surfaces. When the end of the shaft with the latching portion extends through the through hole and beyond the surface of a corresponding mounting foot, the shaft is rotated with respect to the through hole so as to make the latching portion be received in the latching recesses. The blocking surfaces of the latching recesses stop the latching portions rotating with respect to the through hole to escape from the corresponding mounting foot. | 06-02-2011 |
Jin Lu, Radnor, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20100021477 | DESIGN AND GENERATION OF HUMAN DE NOVO pIX PHAGE DISPLAY LIBRARIES - Described and claimed herein are combinatorial synthetic Fab libraries displayed on a phage pIX protein. The libraries were built on scaffolds representing the most frequently used genes in human antibodies, which were diversified to mirror the variability of natural antibodies. After selection using a diverse panel of proteins, numerous specific and high-affinity Fabs were isolated. By a process called in-line maturation the affinity of some antibodies was improved up to one hundred-fold yielding low pM binders suitable for in vivo use. This work thus demonstrates the feasibility of displaying complex Fab libraries as pIX-fusion proteins for antibody discovery and lays the foundations for studies on the structure-function relationship of antibodies. | 01-28-2010 |
| 20110008321 | Vectors, Host Cells, and Methods of Production and Uses - Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids. | 01-13-2011 |
Jin Lu, Manassas, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20080233749 | METHODS AND APPARATUSES FOR REMOVING POLYSILICON FROM SEMICONDUCTOR WORKPIECES - Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other. | 09-25-2008 |
| 20100267239 | METHOD AND APPARATUSES FOR REMOVING POLYSILICON FROM SEMICONDUCTOR WORKPIECES - Methods and apparatuses for removing polysilicon material from a semiconductor workpiece are disclosed. A particular method includes contacting a polishing pad with a semiconductor workpiece having a surface polysilicon material. The method also includes disposing a polishing liquid between the polysilicon material and the polishing pad. The polishing liquid contains an oxidizer that does not include metal elements. The method further includes moving at least one of the semiconductor workpiece and the polishing pad relative to the other while the semiconductor workpiece contacts the polishing pad and the polishing liquid. At least some of the polysilicon material is removed while the polysilicon material contacts the oxidizer in the polishing liquid, as at least one of the semiconductor workpiece and the polishing pad moves relative to the other. | 10-21-2010 |
Jin Lu, Boothwyn, PA US
| Patent application number | Description | Published |
|---|---|---|
| 20080299133 | Anti-Il-12 Antibody Based Vectors, Host Cells, and Methods of Production and Uses - Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids. | 12-04-2008 |
| 20100216234 | Anti-IL-12 Antibody Based Vectors, Host Cells, and Methods of Production and Uses - Antibody expression vectors and plasmids can incorporate various antibody gene portions for transcription of the antibody DNA and expression of the antibody in an appropriate host cell. The expression vectors and plasmids have restriction enzyme sites that facilitate ligation of antibody-encoding DNA into the vectors. The vectors incorporate enhancer and promoter sequences that can be varied to interact with transcription factors in the host cell and thereby control transcription of the antibody-encoding DNA. A kit can incorporate these vectors and plasmids. | 08-26-2010 |
Jin Lu, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090028252 | Combined Frame Alignment and Timing Recovery in OFDM Communications Systems - Timing recovery circuitry for a digital subscriber line (DSL) modem, including a combined frame and timing function for adjusting frame alignment, and for adjusting sample frequency for frequency offset and for phase offset, is disclosed. Frame alignment is adjusted by the frame and timing function by averaging estimates of the phase offset over a plurality of tone pairs within a frame, and then averaging that average estimated phase offset over a plurality of frames to produce a frame offset measurement. Frequency offset is derived by analyzing the extent to which phase error in the received signal varies at a constant rate over time, specifically over a sequence of frames; the sample frequency of the modem is adjusted in response to the detected frequency offset. Phase offset is determined by averaging the phase offset over a plurality of tones within a frame, and integrating differences in this phase offset from frame to frame. The combined frame alignment and sample frequency adjustment may be performed during initialization, or during DSL communications. | 01-29-2009 |
| 20090031197 | ERASURE DECODING FOR RECEIVERS - A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction. | 01-29-2009 |