Patent application number | Description | Published |
20110076851 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 03-31-2011 |
20120276745 | METHOD FOR FABRICATING HOLE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a hole pattern in a semiconductor device includes forming a first organic layer over an etch layer, forming a first inorganic layer pattern over the first organic layer, etching the first organic layer using the first inorganic layer pattern as an etching barrier, forming a second organic layer over the first organic layer, forming a second inorganic layer pattern over the second organic layer, where the second inorganic layer pattern crosses the first inorganic pattern, etching the first and second organic layers using the second inorganic layer pattern as an etching barrier, and etching the etch layer using the etched first and second organic layers as an etch barrier to form a hole pattern. | 11-01-2012 |
20130146958 | METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF - A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines. | 06-13-2013 |
Patent application number | Description | Published |
20090050985 | Semiconductor device with increased channel length and method for fabricating the same - A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer. | 02-26-2009 |
20090159965 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers. | 06-25-2009 |
20090163011 | MASK LAYOUT AND METHOD FOR FORMING VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction. | 06-25-2009 |
20100248434 | Method for Fabricating Semiconductor Device - A method for fabricating a semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region. | 09-30-2010 |
20110207305 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes forming an etch target layer over a substrate including a cell region and a peripheral region, forming a first mask pattern having a first portion and a second portion over the etch target layer in the cell region and forming a second mask pattern having a first portion and a second portion over the etch target layer in the peripheral region, forming a photoresist pattern over the cell region, trimming the first portion of the second mask pattern, removing the photoresist pattern and the second portion of the first mask pattern and the second portion of the second mask pattern, and etching the etch target layer to form a pattern in the cell region and a pattern in the peripheral region. | 08-25-2011 |
Patent application number | Description | Published |
20090087968 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 04-02-2009 |
20090250679 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure. | 10-08-2009 |
20100062581 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - Provided is a method of fabricating a non-volatile semiconductor device. The method includes: forming a first hard mask layer over a substrate; etching the first hard mask layer and the substrate to form a plurality of isolation trenches extending in parallel to one another in a first direction; burying a dielectric layer in the isolation trenches to form a isolation layer; forming a plurality of floating gate mask patterns extending in parallel to one another in a second direction intersecting with the first direction over a resulting structure where the isolation layer is formed; etching the first hard mask layer by using the floating gate mask patterns as an etch barrier to form a plurality of island-shaped floating gate electrode trenches; and burying a conductive layer in the floating gate electrode trenches to form a plurality of island-shaped floating gate electrodes. | 03-11-2010 |
20120007036 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure. | 01-12-2012 |
20120009757 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device includes a lower electrode; and at least two phase-change memory cells sharing the lower electrode. Another phase-change memory device includes a heating layer having a smaller contact area with a phase-change material layer and a greater contact area with a PN diode structure. | 01-12-2012 |
20120184104 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 07-19-2012 |
Patent application number | Description | Published |
20090047788 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of first hard mask patterns at certain intervals over a substrate where an etch target layer is formed, forming a sacrificial layer along a step of the substrate where the first hard mask patterns are formed, forming a second hard mask layer over the sacrificial layer, etching a portion of the second hard mask layer to expose the sacrificial layer and form second hard mask patterns remaining between the first hard mask patterns, removing the sacrificial layer between the first hard mask patterns and the second hard mask patterns, and etching the etch target layer using the first hard mask patterns and the second hard mask patterns as an etch mask. | 02-19-2009 |
20090117742 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a pattern in a semiconductor device includes a single polysilicon hard mask by appropriately selecting spacer material in an SPT, thereby decreasing the number of fabrication processes. Furthermore, since the spacers are easily removed, it is possible to prevent the formation of a step between patterns of a cell region and a peripheral region. | 05-07-2009 |
20090159563 | METHOD FOR FORMING MAGNETIC TUNNEL JUNCTION CELL - A method for forming a magnetic tunnel junction cell includes forming a pinning layer, a pinned layer, a dielectric layer and a free layer over a first electrode, forming a second electrode on the free layer, etching the free layer and the dielectric layer using the second electrode as an etch barrier to form a first pattern, forming a prevention layer on a sidewall of the first pattern, and etching the pinned layer and the pinning layer using the second electrode and the prevention layer as an etch barrier to form a second pattern. | 06-25-2009 |
20090162794 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method includes forming an even number of first hard mask patterns over an etch target layer, forming sacrificial patterns on sidewalls of the first hard mask patterns and forming second hard mask patterns on sidewalls of the sacrificial patterns. The second hard mask patterns are formed to have a first space between the first hard mask patterns. The etch target layer is etched by using the first and the second hard mask patterns. | 06-25-2009 |
20110256354 | MASK LAYOUT AND METHOD FOR FORMING VERTICAL CHANNEL TRANSISTOR IN SEMICONDUCTOR DEVICE USING THE SAME - A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask pattern has openings exposing gaps between each two adjacent pillars in the first direction; etching the insulation layer to a predetermined depth using the mask pattern as an etching barrier to form trenches; and filling the trenches with a conductive material to form word lines extending in the first direction. | 10-20-2011 |