| Patent application number | Description | Published |
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| 20080256305 | MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE - A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system. | 10-16-2008 |
| 20080282042 | Multi-path accessible semiconductor memory device with prevention of pre-charge skip - A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page. | 11-13-2008 |
| 20080313418 | SEMICONDUCTOR MEMORY DEVICE HAVING PROCESSOR RESET FUNCTION AND RESET CONTROL METHOD THEREOF - A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses. | 12-18-2008 |
| 20080320204 | MEMORY SYSTEM AND METHOD WITH FLASH MEMORY DEVICE - A memory system is provided which includes a host, a flash memory device, and a dual port memory which exchanges data with the host and the flash memory device. The flash memory device utilizes a portion of the dual port memory as a working memory. | 12-25-2008 |
| 20090019237 | MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING CONTINUOUS ADDRESS MAP AND METHOD OF PROVIDING THE SAME - A semiconductor memory device for use in a multiprocessor system includes at least two shared memory areas and a row decoder. The at least two shared memory areas are accessible in common by multiple processors of the multiprocessor system through different ports, and assigned based on predetermined memory capacity to a portion of a memory cell array. The row decoder is configured to form a continuous address map for remaining memory portions of the at least two shared memory areas to be dedicated to one port. Each remaining memory portion does not include a corresponding data transfer portion within each shared memory area. | 01-15-2009 |
| 20090024803 | Multipath accessible semiconductor memory device having shared register and method of operating thereof - A semiconductor memory device for use in a multiprocessor system may be provided. A chip size may be controlled, and a design of circuit may be relatively simplified. The semiconductor memory device for use in a multiprocessor system may include at least two shared memory areas commonly accessible by processors of the multiprocessor system through different ports and assigned with a predetermined memory capacity unit to a portion of a memory cell array, a single shared register adapted outside the memory cell array, corresponding to disable areas formed within the shared memory areas, and/or a switching unit for connecting a decoder of a selected shared memory area to the shared register in response to an applied control signal, to match the shared register to the disable area of the selected shared memory area. A shared register may be commonly used in corresponding to a plurality of shared memory areas, thereby reducing or preventing a chip size increase and simplifying a design of the circuit. | 01-22-2009 |
| 20090089487 | MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME - A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array. | 04-02-2009 |
| 20090089545 | MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION - A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor. | 04-02-2009 |
| 20090089573 | MULTI PROCESSOR SYSTEM HAVING DIRECT ACCESS BOOT AND DIRECT ACCESS BOOT METHOD THEREOF - A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise. | 04-02-2009 |
| 20090210691 | Memory System and Memory Management Method Including the Same - A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system. | 08-20-2009 |
| 20090254698 | MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD - A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area. | 10-08-2009 |
| 20100070691 | Multiprocessor system having multiport semiconductor memory device and nonvolatile memory with shared bus - A multiprocessor system employing a multiport semiconductor memory device and a nonvolatile memory having a shared bus is provided. The multiprocessor system includes a first processor; a second processor; a semiconductor memory device including a shared memory area accessed in common by the first and second processors through different ports and assigned within a memory cell array, and an internal register positioned outside the memory cell array, the internal register being configured to provide an access authority for a shared bus to the first and second processors; and a nonvolatile semiconductor memory device having first and second nonvolatile memory areas coupled corresponding to the first and second processors through the shared bus, the first and second nonvolatile memory areas being accessed by and corresponding to the first and second processors according to the access authority for the shared bus. | 03-18-2010 |
| 20100077130 | Multiprocessor system with booting function using memory link architecture - The multiprocessor system includes first and second multiport semiconductor memory devices, first, second and third processors individually storing a first boot loader, the first and second processors being configured to access the first multiport semiconductor memory device, and the second and third processors being configured to access the second multiport semiconductor memory device, and a memory link architecture including the second multiport semiconductor memory device, the third processor, and a nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes a plurality of storage areas storing a second boot loader and software for the first, second and third processors. The third processor is configured to access the nonvolatile semiconductor memory device and configured to apply the second boot loader to the first and second processors through a serial communication to perform a portion of booting the system. | 03-25-2010 |
| 20100095089 | MULTIPROCESSOR SYSTEM WITH MULTIPORT MEMORY - A multiprocessor system includes first and second processors independently executing application functions associated with one or more applications using an open operating system (OS), a multiport memory, a first nonvolatile memory coupled to the first processor via a first bus, and a second nonvolatile memory coupled to the second processor via a second bus. The multiport memory includes a memory cell array divided into a plurality of memory banks including a shared memory bank commonly accessed by the first and second processors via respective first and second ports, and an internal register disposed outside the memory cell array and configured to control access authority to the shared memory bank by the first and second processors, wherein different application functions are independently executed in parallel by the first and second processors using the multiport memory as a data transfer mechanism. | 04-15-2010 |
| 20100185811 | Data processing system and method - A data processing system including a non-volatile memory and a processor controlling an operation of the non-volatile memory is provided. The processor transmits and receives a first type of data to and from an outside through a first path through which a first command and a first address, which are used to write/read the first data to/from the non-volatile memory, are transmitted. The processor also transmits and receives a second type of data to and from the outside through a second path different from the first path through which a second command and a second address, which are used to write/read the second data to/from the non-volatile memory, are transmitted. | 07-22-2010 |
| 20100287424 | Method of writing an operating systems (OS) image to a semiconductor device and the semiconductor device - Example embodiments are directed to a method of writing an Operating System (OS) image to a semiconductor device having a data storage device, an Application Specific Integrated Circuit (ASIC), and a non-volatile memory. The method includes initializing a DRAM interface of the ASIC using a boot loader, receiving the OS image input from a data writer to the semiconductor device through the DRAM interface; and writing the OS image into the non-volatile memory of the semiconductor device using a Flash Translation Layer (FTL) code. | 11-11-2010 |
| 20100318725 | Multi-Processor System Having Function of Preventing Data Loss During Power-Off in Memory Link Architecture - Exemplary embodiments relate to a multi-processor system including: a first processor for writing a power-off check command to a first mail box, reading a power-off wait message or a power-off allowance message written to a second mail box, and waiting or turning off the multi-processor system, in a power-off operation mode; a second processor for indicating whether data is completely stored during a current processing operation in response to the power-off check command in the first mail box and writing the power-off wait message or the power-off allowance message to the second mail box according to the indication result; and a multi-port semiconductor memory device having an internal register that includes the first and second mail boxes and dedicated and shared memory areas for data processing. The first and second mail boxes serve as latch storage units, and the dedicated and shared memory areas are accessed by the first and second processors. | 12-16-2010 |
| 20110013353 | MULTI-CHIP PACKAGE STRUCTURE SUITABLE FOR MULTI-PROCESSOR SYSTEM HAVING MEMORY LINK ARCHITECTURE - A multi-chip package structure can include a first package that includes a first circuit board that includes a lower surface including a first circuit pattern thereon and an upper surface, that is opposite the lower surface, and includes an upper pad layer thereon. The multi-chip package structure can further include at least one processor chip that is mounted on the lower surface of the first circuit board. A second package can be mounted on the first package and can include a second circuit board including an upper surface that includes a second circuit pattern thereon and a lower surface, which is opposite the upper surface, which can includes a lower pad layer thereon that is electrically connected to the upper pad layer of the first circuit board. At least one memory chip can be laminated and molded on the upper surface of the second package. | 01-20-2011 |
| 20110035537 | MULTIPROCESSOR SYSTEM HAVING MULTI-COMMAND SET OPERATION AND PRIORITY COMMAND OPERATION - A multiprocessor system comprises a multi-port semiconductor memory device, a first processor, and a memory link architecture. The multi-port semiconductor memory device comprises a mailbox area and a shared memory area accessible through a plurality of ports. The first processor is configured to write a multi-command set comprising multiple commands for multiple read/write operations to a command area of the shared memory, and to write a message to the mailbox area to indicate the writing of the multi-command set. The memory link architecture comprises a second processor connected to the multi-port semiconductor memory device, and a nonvolatile semiconductor memory device connected to the second processor. The second processor is configured to read the multi-command set from the mailbox area and to sequentially perform the multiple read/write operations according to the multi-command set. | 02-10-2011 |
| 20110035575 | MULTIPROCESSOR SYSTEM COMPRISING MULTI-PORT SEMICONDUCTOR MEMORY DEVICE - A multiprocessor system comprises first and second processors connected to a multi-port semiconductor memory device. The multi-port semiconductor memory device comprises a shared memory area and a plurality of mailbox areas used for inter-processor communication. The first and second processors use a single nonvolatile memory device for storing boot data and transmit information for booting via the shared memory area. | 02-10-2011 |
| 20110047320 | SYSTEM AND METHOD FOR PERFORMING PROGRAM OPERATION ON NONVOLATILE MEMORY DEVICE - A data processing system performs a data processing method by receiving and interpreting a command packet corresponding to a program operation, identifying a size of data to be programmed in the program operation, and programming the data using a buffered or un-buffered program operation based on the size of the data. | 02-24-2011 |
| 20110107049 | METHOD AND APPARATUS ADAPTED TO PREVENT CODE DATA FROM BEING LOST IN SOLDER REFLOW - A semiconductor device comprises a first non-volatile memory configured to store program code and a processor configured to copy the program code from the first non-volatile memory to a second non-volatile memory after a solder reflow process. The processor typically copies the program code from the first non-volatile memory to the second non-volatile memory after the processor is completely booted. | 05-05-2011 |
| 20110167210 | SEMICONDUCTOR DEVICE AND SYSTEM COMPRISING MEMORIES ACCESSIBLE THROUGH DRAM INTERFACE AND SHARED MEMORY REGION - A semiconductor device comprises a nonvolatile memory device, a memory device that processes data according to a DRAM protocol, and an ASIC that converts data output from the memory device into a format compatible with a nonvolatile memory device or a hard disk and outputs the converted data to the nonvolatile memory device or the hard disk. | 07-07-2011 |
