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Jin-Hyo
Jin Hyo Jung, Bucheon-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20090179274 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same is disclosed, in which one line is formed from a main gate to a sidewall gate, so that it is possible to scale a transistor below nano degree, and the semiconductor device includes a semiconductor substrate; a device isolation layer for dividing the semiconductor substrate into a field region and an active region; a main gate on a predetermined portion of the active region of the semiconductor substrate; a sidewall gate at both sides of the main gate on the semiconductor substrate; a main gate insulating layer between the main gate and the semiconductor substrate; a sidewall gate insulating layer between the sidewall gate and the semiconductor substrate; an insulating interlayer between the main gate and the sidewall gate; a first silicide layer on the surface of the main gate and the sidewall gate, to electrically connect the main gate with the sidewall gate; and source and drain regions at both sides of the sidewall gate in the active region of the semiconductor substrate. | 07-16-2009 |
| 20090209082 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer. | 08-20-2009 |
Jin Hyo Jung, Bucheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100029051 | Semiconductor Device and Fabricating Method Thereof - Semiconductor devices and a fabricating method therefore are disclosed. One method includes forming a buffer oxide layer and a buffer nitride layer on the top surface of a semiconductor substrate; forming a photoresist pattern on the pad nitride layer and forming a trench by etching the buffer nitride layer, the buffer oxide layer and the semiconductor substrate by a predetermined etch using the photoresist pattern as a mask; forming sidewall floating gates on the lateral faces of the trench; depositing polysilicon on the entire surface of the resulting structure; forming a gate electrode by patterning the polysilicon of the resulting structure; removing the buffer nitride layer and forming a poly oxide layer on the exposed part of the polysilicon of the gate electrode; forming source/drain regions by implanting impurities into the predetermined part of the resulting structure; injecting electric charges into the sidewall floating gates; and forming spacers on the lateral faces of the sidewall floating gates and the gate electrode. | 02-04-2010 |
Jin Hyo Jung, Boocheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090321823 | Semiconductor Device and Manufacturing Method Thereof - A high voltage semiconductor device and a manufacturing method thereof are provided. The high voltage semiconductor device comprises: second conductive type drift regions disposed spaced from each other on a first conductive type well region formed on a first conductive type semiconductor substrate; a gate electrode on a channel region between the second conductive type drift regions with a gate insulating film disposed therebetween; second conductive type high-concentration source and drain each disposed in the second conductive type drift regions, spaced from a side of a gate electrode; a gate spacer having a spacer part covering the side of the gate electrode and a spacer extending part to cover a spaced portion of the second conductive type high-concentration source and drain from the side of the gate electrode; and a silicide formed on the gate electrode and the second conductive type high-concentration source and drain. | 12-31-2009 |
Jin Hyo Jung, Bucheon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090206382 | FLASH MEMORY DEVICE AND PROGRAMMING AND ERASING METHODS THEREWITH - A flash memory device and programming and erasing methods therewith is disclosed, to secure the programming and erasing characteristics by changing a structure of a floating gate, in which the flash memory device includes a first conductive type semiconductor substrate defined as a field area and an active area; a tunnel oxide layer on the active area of the first conductive type semiconductor substrate; a floating gate on the tunnel oxide layer, having at least first and second floating gates having different levels of energy band gap; a dielectric layer on the floating gate; a control gate on the dielectric layer; and second conductive type source/drain regions in the active area of the first conductive type semiconductor substrate at both sides of the floating gate. | 08-20-2009 |
Jin Hyo Kim, Geoje-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080209908 | APPARATUS AND METHOD FOR LIQUEFIED NATURAL GAS CARRIER PROPULSION - Disclosed herein is an apparatus and method for liquefied natural gas (LNG) carrier propulsion. In the apparatus and method, the propulsion of an LNG carrier is done by only a single main diesel engine and has construction to promptly cope with emergencies caused by malfunction of the main diesel engine. The propulsion apparatus for an LNG carrier comprising a boil-off gas re-liquefaction apparatus for re-liquefying boil-off gas generated in LNG storage tanks to return re-liquefied boil-off gas back to the LNG storage tank comprises a single main diesel engine, a propulsion shaft separably connected to the main diesel engine, and an electric motor for propulsion separably connected to the propulsion shaft and supplied with power intended for operation of the boil-off gas re-liquefaction apparatus. | 09-04-2008 |
Jin Hyo Kim, Gyeongsangnam-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090252694 | Novel Chalcone Derivatives, Pharmaceutically Acceptable Salt, Method for Preparation and Uses Thereof - Disclosed relates to a novel chalcone derivative, pharmaceutically acceptable salt thereof, a method for preparing the same and uses thereof, the chalcone derivative being readily obtained through the steps of: reacting aminoacetophenone with sulfonylchloride under the presence of an appropriate salt; and reacting the compound prepared in the above step with hydroxybenzaldehide under the presence of an appropriate catalyst. The chalcone derivative of formula 1 in accordance with the present invention having strong enzyme inhibitory activities for glycosidase can be effectively used in preventing and treating various diseases induced by glycosidase, and the chalcone derivative of the invention having tyrosinase and melanin synthesis inhibitory activities can be effectively used as a skin-whitening compound. | 10-08-2009 |
Jin-Hyo Jung, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090166717 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a nonvolatile memory device and a method for manufacturing the same. According to embodiments, a nonvolatile memory device may include a tunnel ONO film having an oxide film, a nitride film, and an oxide film stacked on and/or over a semiconductor substrate. It may also include a trap nitride film formed on and/or over the tunnel ONO film, a blocking oxide film formed on and/or over the trap nitride film and having a high-dielectric film with a higher dielectric constant than a dielectric constant of a SiO | 07-02-2009 |
| 20100157690 | Semiconductor Memory Device of Single Gate Structure - A single gate semiconductor memory device includes a high-potential well on an upper portion of a semiconductor substrate; a first well on an upper portion of the high potential second conductive type well; a second well spaced apart from the first well on the upper portion of the high potential well and across the high-potential well; a floating gate on the first well and the second well; a first ion implantation region in the first well on one side of the floating gate; a second ion implantation region in the first well on an opposite side of the floating gate; a first complementary ion implantation region in the first well next to the second ion implantation region; a third ion implantation region in the second well on one side of the floating gate; and a second complementary ion implantation region in the second well on the opposite side of the floating gate. | 06-24-2010 |
| 20100165745 | NON-VOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - A non-volatile memory device and a driving method thereof. The non-volatile memory device includes a floating gate formed on and/or over a first type well, and transistors formed on and/or over a second type well and connected in series to the floating gate. One of the transistors is a first transistor for program and erase operations, and the other one is a second transistor for a reading operation. | 07-01-2010 |
Jin-Hyo Jung, Gangnam-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20100165746 | SEMICONDUCTOR MEMORY CELL, METHOD FOR MANUFACTURING THE SAME AND METHOD FOR OPERATING THE SAME - A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a control gate, and/or grounding a word line and/or a bit line. A method of operating may include erasing a semiconductor memory cell by floating and/or grounding a word line, applying a preset erase voltage to a control gate, and/or grounding an N-well, a bit line and/or a common source. A method of operating may include reading a semiconductor memory cell by grounding and/or floating a control gate, applying a preset read voltage to an N-well and/or a common source, grounding a word line, and/or applying a preset drain voltage to a bit line. | 07-01-2010 |
Jin-Hyo Kim, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110093724 | APPARATUS AND METHOD FOR POWER CONTROL OF A CENTRAL PROCESSING UNIT IN A MULTI-CORE SYSTEM - A power control method of a Central Processing Unit (CPU) in a multi-core system. The power control method includes acquiring current usage information of the CPU and system information, estimating a CPU usage of a next time interval based on the acquired current usage information, calibrating the estimated CPU usage of the next time interval based on the acquired system information, and determining a power control mode based on at least one of the acquired system information and the calibrated CPU usage of the next time interval. | 04-21-2011 |
Jin-Hyo Park, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110126153 | DISPLAY DEVICE AND METHOD OF CONTROLLING THE SAME - The display device according to the proposed embodiment is configured to include a screen unit that includes a display unit to display a menu image and a sensing unit to sense a user screen touch; a memory unit that stores the menu image displayed on the screen unit; and if the screen touch is sensed by the sensing unit, a controller that displays the stored menu image on the sensed touch point, wherein the controller determines directions where the menu image is to be displayed according to the sensed touch point. | 05-26-2011 |