| Patent application number | Description | Published |
|---|
| 20090010052 | One-transistor type dram - A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. | 01-08-2009 |
| 20090010054 | SEMICONDUCTOR MEMORY DEVICE WITH FERROELECTRIC DEVICE - A semiconductor memory device includes a one-transistor (1-T) field effect transistor (FET) type memory cell connected between a pair of bit lines, and controlled by a word line, where a different channel resistance is induced to a channel region depending on a polarity state of a ferroelectric layer. The device comprises a plurality of word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a pair of clamp dummy lines arranged in the column direction, a pair of reference dummy lines arranged in the column direction, a cell array including the memory cell and formed in a region where the word line and the bit line are crossed, a dummy cell array including the memory cell and formed where the word line, the pair of claim dummy lines and the pair of reference dummy lines are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. | 01-08-2009 |
| 20090010079 | One-transistor type dram - A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages. | 01-08-2009 |
| 20090043973 | Phase change memory device - A phase change memory device comprises a cell array unit including a phase change resistance cell disposed in a region where a word line and a bit line are crossed, a sense amplifier configured to sense and amplify data of the phase change resistance cell, a write driving unit configured to supply a write voltage corresponding to data to be written in the cell array unit in response to an enabling signal, and a write verifying control unit controlled by an activation control signal and configured to compare data read through the sense amplifier with the data to be written so as to output the enabling signal. | 02-12-2009 |
| 20100020622 | ONE-TRANSISTOR TYPE DRAM - A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. | 01-28-2010 |
| 20100046308 | ONE-TRANSISTOR TYPE DRAM - A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages. | 02-25-2010 |
| 20110101917 | BATTERY PACK - A battery pack includes a case including external terminals, batteries disposed in the case, and balancing lines connected to each of the batteries and functioning as pathways of a voltage signal transmitted to a controller. At least one of the balancing lines functions as a high current line supplying battery current to the external terminals. Thus, the battery pack may have a simple structure and may be simply assembled using the high current line as a balancing line. | 05-05-2011 |
| 20110101921 | BATTERY PACK - Battery pack circuits are provided. In one embodiment, the invention relates to a battery pack including a rechargeable battery including a first battery terminal and a second battery terminal coupled to a common terminal, a discharge control switch coupled between the first battery terminal and a first discharging terminal, a charge control switch coupled between the first discharging terminal and a first charging terminal, wherein the battery pack is configured to provide a current to a load coupled between the first discharging terminal and the common terminal, and a processing circuitry configured to charge and discharge the battery by controlling the discharge control switch and the charge control switch. | 05-05-2011 |
