Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Jin Gu
Jin Gu Kang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100055568 | TRANSITION METAL OXIDES/MULTI-WALLED CARBON NANOTUBE NANOCOMPOSITE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a transition metal oxide/multi-walled carbon nanotube nanocomposite and its preparation method, and particularly to a nanocomposite prepared in a composite form of an electron-transmitting and stress-relaxing one-dimensional multi-walled carbon nanotube (MWCNT) and a high-capacity-enabling zero-dimensional nanopowder-type transition metal oxide, where a transition metal oxide prepared by urea synthesis is uniformly dispersed in a carbon nanotube by a surfactant, and its preparation method. | 03-04-2010 |
| 20110165461 | ELECTRODE INCLUDING NANOCOMPOSITE ACTIVE MATERIAL, METHOD OF PREPARING THE SAME, AND ELECTROCHEMICAL DEVICE INCLUDING THE SAME - The present invention provides an electrode and a method of preparing the same. The electrode of the present invention is prepared by forming a nanostructured conductor comprising a metal or metal oxide on a substrate and forming an active material comprising metal oxide nanoparticles on the surface of the nanostructured conductor. The electrode of the present invention can be used in various electrochemical devices such as energy storage devices including secondary batteries, supercapacitors, etc., photocatalyst elements, thermoelectric elements, or composite elements thereof. Moreover, the electrode of the present invention can be applied to a lithium secondary battery, in which intercalation/deintercalation of lithium ions is performed, and especially applied to a negative electrode of the lithium secondary battery. | 07-07-2011 |
Jin Gu Kang, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20110123419 | METHOD FOR PREPARING MANGANESE SULFATE AND ZINC SULFATE FROM WASTE BATTERIES CONTAINING MANGANESE AND ZINC - A method for preparing manganese sulfate and zinc sulfate from waste batteries containing manganese and zinc, and more particularly to a method for preparing manganese sulfate and zinc sulfate from waste batteries containing manganese and zinc. Zinc powder and activated carbon are added to a leached solution obtained from a continuous leaching process so as to remove heavy metals and organic materials from the leached solution, and then the leached solution is spray-dried to simultaneously obtain manganese sulfate and zinc sulfate at high-purity by a simple process without generating wastewater. An environmentally friendly waste battery recycling process is thereby provided, because it is not required to use additional chemical substances for neutralization titration or impurity removal in recovering manganese sulfate and zinc sulfate by leaching a waste battery powder. | 05-26-2011 |
Jin Gu Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080217789 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING METAL LINE OF SEMICONDUCTOR DEVICE - A semiconductor device and a method of forming a metal line of a semiconductor device includes a first insulating layer formed over a semiconductor substrate an etch-stop layer formed over the first insulating layer, contact holes formed by etching the etch-stop layer and the first insulating layer, Contact plugs formed within the contact holes and a second insulating layer formed over the contact plugs and the etch-stop layer. The second insulating layer is etched in order to form trenches through which the contact plugs are exposed. Metal lines are formed within the trenches. Accordingly, since a hard mask with a high dielectric constant does not remain between the metal lines, the capacitance of the metal lines can be reduced. | 09-11-2008 |
| 20090073667 | Semiconductor chip package and printed circuit board - A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip. | 03-19-2009 |
| 20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
| 20100144152 | Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer. | 06-10-2010 |
| 20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
| 20100159646 | Method of manufacturing wafer level package - The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units. | 06-24-2010 |
| 20110201156 | Method of manufacturing wafer level package including coating resin over the dicing lines - A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units. | 08-18-2011 |
Jin Gu Kim US
| Patent application number | Description | Published |
|---|---|---|
| 20110129960 | Method of manufacturing stacked wafer level package - A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes. | 06-02-2011 |
Jin Gu Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110207287 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming a charge trap layer, including first impurity ions of a first concentration, over the tunnel insulating layer, forming a compensation layer, including second impurity ions of a second concentration, over the charge trap layer, diffusing the second impurity ions within the compensation layer toward the charge trap layer, removing the compensation layer, forming a dielectric layer on surfaces of the charge trap layer, and forming a conductive layer for a control gate on the dielectric layer. | 08-25-2011 |
Jin Gu Park, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20100291533 | INDOLE AND INDAZOLE DERIVATIVES HAVING A CELL-, TISSUE- AND ORGAN-PRESERVING EFFECT - The present invention relates to a composition for preserving cells, tissues and organs, comprising as an active ingredient indole and indazole compounds of formula (1), or a pharmaceutically acceptable salt or isomer thereof, which are effective for preventing injury of organs, isolated cell systems or tissues caused by cold storage, transplant operation or post-transplantation reperfusion; a preservation method; and a preparation method of the composition. | 11-18-2010 |