| Patent application number | Description | Published |
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| 20090031153 | Power Management Server for Managing Power Consumption - A power management server and method for managing power consumption is disclosed. According to one embodiment, a power management server data processing system is provided, where the power management server data processing system comprises a power management communication port to communicatively couple the power management server data processing system to a power-managed server data processing system and a system management processor coupled to the power management communication port. In the described embodiment, the system management processor comprises power management logic configured to receive power management data from the power-managed server data processing system, to generate a power management command utilizing the power management data, and to transmit the power management command to the power-managed server data processing system utilizing the power management communication port. Moreover, the power management data of the described embodiment comprises power management capability data. | 01-29-2009 |
| 20090091186 | SYSTEM AND METHOD FOR MULTIPLE SENSE POINT VOLTAGE REGULATION - The present invention is a system and method for sensing the voltage at multiple sense points. The present invention acquires optimal feedback from a plurality of sources including those integrated on the same motherboard, for populated or unpopulated connectors and for adapter cards plugged into the connectors, for the purpose of controlling the voltage regulator output. The voltage regulator, connected to a logic system, provides voltage to those connectors needing the voltage. | 04-09-2009 |
| 20090157920 | Dynamically Allocating Communication Lanes For A Plurality Of Input/Output ('I/O') Adapter Sockets In A Point-To-Point, Serial I/O Expansion Subsystem Of A Computing System - Methods, systems, and products are disclosed for dynamically allocating communication lanes for a plurality of sockets in a point-to-point, serial I/O expansion subsystem of a computing system, the expansion subsystem including an switch that supports a maximum number of enabled communication lanes, each socket having a same form factor, each socket connected to the switch using a same predefined number of communication lanes, that include: identifying, during a boot process for the computing system, each of the sockets in which an adapter is installed; determining, for each installed adapter, a maximum link width for that adapter; and enabling, for each of the sockets in which an adapter is installed, a set of communication lanes for communications between the adapter installed in that socket and the expansion subsystem switch in dependence upon the maximum link width for each adapter and the maximum number of enabled communication lanes supported by the switch. | 06-18-2009 |
| 20090164846 | Fault Injection In Dynamic Random Access Memory Modules For Performing Built-In Self-Tests - Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module. | 06-25-2009 |
| 20100293410 | Memory Downsizing In A Computer Memory Subsystem - Memory downsizing in a computer memory subsystem, the subsystem including one or more channels of computer memory with each channel including several Dual In-line Memory Modules (‘DIMMs’) and each DIMM capable of on-die termination (‘ODT’). Memory downsizing according to embodiments of the present invention includes identifying, during a memory initialization test in a Power On Self Test (‘POST’) by a firmware module, a defective DIMM of a particular channel in the computer memory subsystem and disabling, by the firmware module, the defective DIMM, including enabling ODT for the defective DIMM without disabling any non-defective DIMMs. | 11-18-2010 |
| 20110080700 | Airflow Barriers for Efficient Cooling of Memory Modules - Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load. | 04-07-2011 |
| 20110160916 | Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack - Computing devices have fan speeds governing airflows through the computing devices. The rack has a maximum airflow associated with a cooling component for the rack. The computing devices transmit their current airflows. A sum of the current airflows is determined. Where the sum is greater than the maximum airflow, the fan speeds of one or more selected computing devices are decreased. The fan speeds of lower priority computing devices may be reduced before the fan speeds higher priority computing devices are reduced. Fan speed reduction may be achieved in a centralized manner, by employing a centralized management component, or in a decentralized manner, without employing a centralized management component. | 06-30-2011 |
| Patent application number | Description | Published |
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| 20110108972 | Integrated Circuit Die Stacks With Translationally Compatible Vias - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die. | 05-12-2011 |
| 20110109381 | Integrated Circuit Die Stacks With Rotationally Symmetric Vias - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (TSVs') in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die. | 05-12-2011 |
| 20110110064 | Integrating Circuit Die Stacks Having Initially Identical Dies Personalized With Fuses - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die. | 05-12-2011 |
| 20110110065 | Integrated Circuit Die Stacks Having Initially Identical Dies Personalized With Switches - Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by opening switches on the first die, converting the TSVs previously connected through the open switches into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by opening switches on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die. | 05-12-2011 |
