| Patent application number | Description | Published |
|---|
| 20080290930 | LOW VOLTAGE CHARGE PUMP - A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor. | 11-27-2008 |
| 20080290955 | LOW COST AND LOW VARIATION OSCILLATOR - An oscillator circuit for use in integrated circuits. The oscillator circuit includes a delay generation circuit having a current mirror with at least a first current mirror branch and a second current mirror branch, a current source coupled to the first current mirror branch, a capacitive element coupled to the first current mirror branch; and a resistive element coupled to the second current mirror branch. The oscillator circuit further includes a plurality of inverting elements coupled in series with one another and a transconducting element coupled to an output of the plurality of inverting elements. The transconducting element is configured to discharge the capacitive element. A latching element is coupled to latch to an output signal of the plurality of inverting elements. | 11-27-2008 |
| 20090073781 | Sense Amplifier - A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation. | 03-19-2009 |
| 20090108913 | MOS RESISTOR WITH SECOND OR HIGHER ORDER COMPENSATION - A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference. | 04-30-2009 |
| 20090153232 | Low voltage charge pump - A single pump stage of a multi-stage charge pump couples a first low-voltage NMOS transistor in series with a first low-voltage PMOS transistor between charge transfer capacitors. A second low-voltage NMOS transistor is coupled between the gate and the source of the first NMOS transistor. A second low-voltage PMOS transistor is coupled between the gate and the source of the first PMOS transistor. Respective boost voltages are applied to gates of the first NMOS transistor and the second PMOS transistor to minimize threshold voltage losses. A stabilizing capacitor is connected between the first NMOS transistor and the second PMOS transistor. | 06-18-2009 |
| 20100008159 | Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage. | 01-14-2010 |
| 20100052840 | LOW VARIATION RESISTOR - This document discloses low variation resistor devices, methods, systems, and methods of manufacturing the same. In some implementations, a low-variation resistor can be implemented with a metal-oxide-semiconductor field-effect-transistor (“MOSFET”) operating in the triode (e.g., ohmic) region. The MOSFET can have a source that is connected to a reference voltage (e.g., ground) and a gate connected to a gate voltage source. The gate voltage source can generate a gate voltage that varies in proportion to changes in the temperature of an operating environment. The gate voltage variation can, for example, be controlled so that it offsets the changes in MOSFET resistance that are caused by changes in temperature. In some implementations, the gate voltage variation offsets the resistance variance by offsetting changes in transistor mobility that are caused by changes in temperature. | 03-04-2010 |
| 20100201430 | MOS Resistor with Second or Higher Order Compensation - A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference. | 08-12-2010 |
| 20100208539 | VOLTAGE REGULATOR FOR MEMORY - A circuit includes a first negative feed back loop coupled to a virtual Vvdd power rail and a true Vdd power rail. A second negative feed back loop is coupled to the virtual Vvss power rail and a true Vss power rail. The virtual rail to virtual rail voltage difference is regulated at the highest threshold voltage between pull-up and pull-down transistors of a memory cell. | 08-19-2010 |
| 20100329023 | SENSE AMPLIFIER APPARATUS AND METHODS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell. Additional embodiments are disclosed. | 12-30-2010 |
| 20100329059 | APPARATUS AND METHODS FOR SENSE AMPLIFIERS - Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to carry a current having a value based on a value of information stored in the memory cell; and a second circuit including a second circuit path coupled between the supply node and the line to charge the line during the memory operation. Additional embodiments are disclosed. | 12-30-2010 |
| 20110026347 | Differential Sense Amplifier - A differential sense amplifier can perform data sensing using a very low supply voltage. | 02-03-2011 |
| 20110115560 | DIFFERENTIAL PAIR WITH CONSTANT OFFSET - A bias current is generated for an unbalanced differential pair that is proportional to the transconductance gain of the differential pair. When the transconductance gain varies (e.g., due to temperature variations), the bias current varies in proportion thereby maintaining a constant offset voltage. In some implementations, a voltage to current converter circuit generates the bias current from a constant reference voltage that is independent of temperature and voltage supply variations (e.g., a bandgap reference voltage). | 05-19-2011 |
