Patent application number | Description | Published |
20120238316 | MOBILE PHONE AND COMMUNICATION SYSTEM SWITCHING METHOD - A mobile phone includes two different communication systems and a current table storing relationship between signal transmission power and current in relation to the two different communication systems. The mobile phone obtains two received signal strength indications (RSSI) in relation to the two different communication systems if the mobile phone requires the voice call service, and then calculates two signal transmission power in relation to the two communication system according to the two RSSI. The mobile phone searches a current table to obtain two current according to the two signal transmission power. The mobile phone compares the two current to select one of the two communication systems which needs a smaller one of the two current to provide the voice call service. | 09-20-2012 |
20140291764 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal. | 10-02-2014 |
20140291765 | ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference. | 10-02-2014 |
20140339614 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - The present invention provides an image sensor and a method of fabricating the same. The image sensor comprises a semiconductor substrate, a photosensitive component, and a pixel-readout circuit, characterized in that, the semiconductor substrate comprises a supporting substrate, a first insulating buried layer, a first semiconductor layer, a second insulating buried layer, and a second semiconductor layer covered on the semiconductor substrate in sequence; the first semiconductor layer and the second semiconductor layer have different thicknesses, such that the photosensitive component is in the thicker semiconductor layer, and the pixel-readout circuit is in the thinner semiconductor layer. To realize the image sensor mentioned above, two different methods are provided. Ion implantation and bonding method are used respectively to provide the first and second insulating buried layers, and the first and second semiconductor layer substrates, and then the image sensor is fabricated. The image sensor in the present invention has a well anti-radiation character and a well semiconductor character, and a photosensitive zone that has higher light absorption rate. | 11-20-2014 |
20150015731 | APPARATUS AND METHOD TO REDUCE PTZ LATENCY - An apparatus, system, and method to reduce PTZ latency are provided. The system can include an input port and a motor driver unit, and the input port can receive a PTZ request. The input port can transmit the PTZ request to the motor driver unit, and the motor driver unit can extract a PTZ command from the PTZ request. In some embodiments, the PTZ request can obviate transmission through a parser and a processor. | 01-15-2015 |
20150137881 | High-Voltage-Tolerant Pull-Up Resistor Circuit - A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage. | 05-21-2015 |
20150252391 | METHOD USING MICROALGAE FOR HIGH-EFFICIENCY PRODUCTION OF ASTAXANTHIN - The present invention relates to a novel method for producing astaxanthin by using microalgae. The method comprises: heterotrophic cultivation of microalgae, dilution, photo-induction, collection of microalgal cells, and extraction of astaxanthin. The method according to the present invention takes full advantages of rapid growth rate in the heterotrophic stage and fast accumulation of astaxanthin in the photo-induction stage by using a large amount of microalgal cells obtained in the heterotrophic cultivation stage, so as to greatly improve the astaxanthin production rate and thereby achieve low cost, high efficiency, large scale production of astaxanthin by using microalgae. The method not only provides an important technical means to address the large scale industrial production of astaxanthin through microalgae but also ensures an ample source of raw material for the widespread utilization of astaxanthin. | 09-10-2015 |
20150270234 | PAD STRUCTURE FOR SEMICONDUCTOR DEVICE CONNECTION - A pad structure may include a conductive pad that includes an exposed portion. The pad structure may further include a first conductive set that includes a first conductive part and a second conductive part. The first conductive part may overlap the exposed portion in a direction perpendicular to the conductive pad. The first conductive part may be spaced from the second conductive part in a direction parallel to the conductive pad and may overlap the second conductive part in the direction parallel to the conductive pad. The pad structure may further include a conductive layer that contacts the conductive pad and is positioned between the conductive pad and the first conductive set in the direction perpendicular to the conductive pad. The pad structure may further include a first via member, which may electrically connect the first conductive part to the conductive layer. | 09-24-2015 |