Patent application number | Description | Published |
20130021768 | CHIP-ON-FILM PACKAGES AND DEVICE ASSEMBLIES INCLUDING THE SAME - Chip-on-film packages are provided. A chip-on-film package includes a film substrate having a first surface and a second surface opposite to each other, a semiconductor chip on the first surface, and a thermal deformation member adjacent to the second surface. The thermal deformation member has a construction that causes its shape to transform according to a temperature. Related devices and device assembles are also provided. | 01-24-2013 |
20130057559 | DISPLAY DEVICES - A display device includes a panel including pixels defined by data lines and gate lines, a housing chassis covering a sidewall and an edge of the panel, a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal, a chip on film connecting the printed circuit board to the panel, the chip on film between the housing chassis and the sidewall of the panel, a driver integrated circuit mounted on the chip on film and configured to respond to the control signal and drive at least one of the data signal and the gate signal applied to the data lines and the gate lines, and a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis. | 03-07-2013 |
20130091348 | SURFACE TEMPERATURE MANAGEMENT METHOD OF MOBILE DEVICE AND MEMORY THERMAL MANAGEMENT METHOD OF MULTICHIP PACKAGE - A surface temperature management method of mobile device is provided. The method includes sensing a temperature of an application processor in an operation mode of the mobile device; and controlling the application processor using the sensed temperature and a surface temperature management table to manage a surface temperature of a target part of the mobile device. The surface temperature management table includes information related to the temperature of the application processor corresponding to the surface temperature of the target part in the operation mode. | 04-11-2013 |
20130139524 | THERMOELECTRIC COOLING PACKAGES AND THERMAL MANAGEMENT METHODS THEREOF - Provided are thermoelectric cooling packages and thermal management methods thereof. The method may include measuring a temperature of the thermoelectric cooling package including a semiconductor chip and a thermoelectric cooler, comparing the temperature of the thermoelectric cooling package with a target temperature, operating the thermoelectric cooler when the temperature of the thermoelectric cooling package is higher than the target temperature, and stopping the operation of the thermoelectric cooler when the temperature of the thermoelectric cooling package becomes lower than the target temperature. | 06-06-2013 |
20130166093 | ELECTRONIC DEVICE AND TEMPERATURE CONTROL METHOD THEREOF - An electronic device may be operated in any of a plurality of heat-dissipation modes to accommodate temperature rises, including rapid temperature rises, while allowing an electronic device to continue operating. A parameter such as clock frequency, a supply voltage, current consumption, the number of applications running, or other operating parameter, may be manipulated to control internal heat dissipation and thereby accommodate factors, such as external temperature rises. One operation mode may be a maximum operation mode in which clock(s) operate at their highest frequencies and power is supplied at its highest level. A shut-down operation mode, in which a processor cuts power to electronic components, may be entered when a temperature of interest exceeds a predetermined threshold. | 06-27-2013 |
20140367860 | SEMICONDUCTOR PACKAGES INCLUDING HEAT DIFFUSION VIAS AND INTERCONNECTION VIAS - A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via. | 12-18-2014 |
20150115467 | PACKAGE-ON-PACKAGE DEVICE - The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns. | 04-30-2015 |