Patent application number | Description | Published |
20110271014 | DIRECT I/O DEVICE ACCESS BY A VIRTUAL MACHINE WITH MEMORY MANAGED USING MEMORY DISAGGREGATION - Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the physical address to a machine address, and the physical address used as part of a DMA operation generated by an I/O device that is programmed by a VM. It also includes transmitting data associated with the memory page as part of a memory disaggregation regime, the memory disaggregation regime to include an allocation of an additional memory page, on a remote memory device, to which the data will be written. It further includes updating a P2M translation table associated with the hypervisor, and an IOMMU translation table associated with the I/O device, to reflect a mapping from the physical address to a machine address associated with the remote memory device and used to identify the additional memory page. | 11-03-2011 |
20110307679 | MANAGING WEAR ON INDEPENDENT STORAGE DEVICES - In a method of managing wear on a plurality of independent storage devices having respective sets of memory cells, access characteristics of the memory cells in the plurality of independent storage devices are monitored. In addition, an instruction to access data on at least one of the memory cells is received and an independent storage device of the plurality of independent storage devices is selected to access data on at least one of the memory cells of the selected independent storage device based upon one or more predetermined selection policies and the monitored access characteristics of the memory cells in the plurality of independent storage devices. Moreover, the selected independent storage device is assigned to access data on at least one of the memory cells of the selected independent storage device according to the received instruction. | 12-15-2011 |
20120087674 | OPTICAL DATA PATH SYSTEMS - This disclosure is directed to optical data path systems that enable unidirectional and bidirectional transmission of optical signals between nodes of a multi-node system such as a multiprocessor system. In one aspect, an optical data path system includes an optical device layer connected to nodes of a multi-node system and a controller. The optical device layer includes a waveguide network of waveguide branches optically connecting each node of the multi-node system to every other node of the multi-node system, resonators disposed adjacent to the waveguide branches, and detectors disposed adjacent to waveguide branches of the waveguide network. Each detector is electronically connected to a node of the multi-node system. The resonators are operated by the controller to control the path of optical signals sent between the nodes of the multi-node system. | 04-12-2012 |
20120096052 | Managing a Data Structure - In a method for managing a data structure in a memory, an accessor to access a version of the data structure is determined, in which the accessor includes a version number and a fat pointer, in which the version number corresponds to the most recent version of the data structure, and wherein the fat pointer is configured to enable for multiple versions of a linked-data structure to be maintained. | 04-19-2012 |
20120185727 | COMPUTING SYSTEM RELIABILITY - Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices. | 07-19-2012 |
20120203381 | MANAGING AN INFRASTRUCTURE HOUSING DISAGGREGATED HEAT SOURCES - In a method for managing an infrastructure housing a plurality of disaggregated heat sources, in which a first disaggregated heat source has different heat dissipation characteristics as compared with a second disaggregated heat source, cooling requirements for the disaggregated heat sources are determined, in which the first disaggregated heat source and the second disaggregated heat source are to be positioned in separate homogeneous zones of the infrastructure. In addition, a respective available cooling resource is associated with the disaggregated heat sources based upon the determined cooling requirements of the disaggregated heat sources. | 08-09-2012 |
20120210042 | REMOTE MEMORY FOR VIRTUAL MACHINES - Remote memory can be used for a number idle pages located on a virtual machine. A number of idle pages can be sent to the remote memory according to a placement policy, where the placement policy can include a number of weighting factors. A hypervisor on a computing device can record a local size and a remote page fault frequency of the number of virtual machines. The hypervisor can scan local memory to determine the number of idle pages and a number of idle virtual machines. The number of idle pages, including a page map and a remote address destination for each idle page, can be sent to the remote memory by the hypervisor. The number of virtual machines can be analyzed to determine a per-virtual machine local memory allocation. | 08-16-2012 |
20120254507 | WRITE-ABSORBING BUFFER FOR NON-VOLATILE MEMORY - A write-absorbing, volatile memory buffer for use with a processor module and a non-volatile memory is disclosed. The write-absorbing buffer operates as a dirty cache that can be used to look up both read and write requests, although allocating new blocks only for write requests and not read requests. The blocks are small sized, and a write-only least-recently used cache replacement policy is used to transfer data in the blocks to the non-volatile memory. The write-absorbing buffer can be used to store copy-on-write pages for at least one virtual machine associated with the processor module and reduce write overhead to the non-volatile memory. | 10-04-2012 |
20120268983 | RANDOM-ACCESS MEMORY WITH DYNAMICALLY ADJUSTABLE ENDURANCE AND RETENTION - A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality. | 10-25-2012 |
20120272036 | ADAPTIVE MEMORY SYSTEM - An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations. | 10-25-2012 |
20120272039 | RETENTION-VALUE ASSOCITED MEMORY - A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address. | 10-25-2012 |
20120278650 | CONTROLLING NANOSTORE OPERATION BASED ON MONITORED PERFORMANCE - Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore. | 11-01-2012 |
20120278651 | Remapping data with pointer - Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block. | 11-01-2012 |
20130054869 | METHODS AND APPARATUS TO ACCESS DATA IN NON-VOLATILE MEMORY - Example methods, apparatus, and articles of manufacture to access data are disclosed. A disclosed example method involves generating a key-value association table in a non-volatile memory to store physical addresses of a data cache storing data previously retrieved from a data structure. The example method also involves storing recovery metadata in the non-volatile memory. The recovery metadata includes a first address of the key-value association table in the non-volatile memory. In addition, following a re-boot process, the locations of the key-value association table and the data cache are retrieved using the recovery metadata without needing to access the data structure to re-generate the key-value association table and the data cache. | 02-28-2013 |
20130094138 | COMPUTER RACKS - Example computer racks to improve environmental sustainability in data centers are disclosed. An example computer rack includes a spine ( | 04-18-2013 |
20130111055 | DATA STREAM OPERATIONS | 05-02-2013 |
20130111107 | TIER IDENTIFICATION (TID) FOR TIERED MEMORY CHARACTERISTICS | 05-02-2013 |
20130111164 | HARDWARE COMPRESSION USING COMMON PORTIONS OF DATA | 05-02-2013 |
20130111249 | ACCESSING A LOCAL STORAGE DEVICE USING AN AUXILIARY PROCESSOR | 05-02-2013 |
20130290607 | STORING CACHE METADATA SEPARATELY FROM INTEGRATED CIRCUIT CONTAINING CACHE CONTROLLER - A technique includes using a cache controller of an integrated circuit to control a cache including cached data content and associated cache metadata. The technique includes storing the metadata and the cached data content off of the integrated circuit and organizing the storage of the metadata relative to the cached data content such that a bus operation initiated by the cache controller to target the cached data content also targets the associated metadata. | 10-31-2013 |
20130290650 | DISTRIBUTED ACTIVE DATA STORAGE SYSTEM - A request from a requestor identifies data stored in a distributed active data storage system and a procedure that is associated with the identified data for a given node of the distributed active data storage system to execute. The execution of the procedure causes the given node to selectively determine an address for routing another request to an element of a plurality of elements of a data structure stored on the plurality of nodes. | 10-31-2013 |
20130329491 | Hybrid Memory Module - A hybrid. memory module. The module includes at least two heterogeneous memory devices and a memory buffer in communication with the memory devices to read data from any one of the memory devices and write the data to any other of the memory devices. | 12-12-2013 |
20130339468 | NON-VOLATILE MEMORY PHYSICAL NETWORKS - A method for communication between computing devices includes identifying the parameters of a data transfer between a source computing device and a target computing device and identifying communication paths between a source computing device and target computing device, in which at least one of the communications paths is a physical network. A communication path is selected for the data transfer. When a data transfer over the physical network is selected as a communication path, a nonvolatile memory (NVM) unit is removed from the source computing device and placed in a cartridge and the cartridge is programmed with transfer information. The NVM unit and cartridge are transported through the physical network to the target computing device according to the transfer information and the NVM unit is electrically connected to the target computing device. | 12-19-2013 |
20140013054 | STORING DATA STRUCTURES IN CACHE - A method and system for implementing a data structure cache are provided herein. The method includes identifying a data structure. The method also includes identifying a plurality of frequently accessed data blocks in the data structure. Additionally, the method includes reserving a portion of a cache for storage of the frequently accessed data blocks. Furthermore, the method includes storing the frequently accessed data blocks in the reserved portion of the cache. | 01-09-2014 |
20140019677 | STORING DATA IN PRESISTENT HYBRID MEMORY - Storing data in persistent hybrid memory includes promoting a memory block from non-volatile memory to a cache based on a usage of said memory block according to a promotion policy, tracking modifications to the memory block while in the cache, and writing the memory block back into the non-volatile memory after the memory block is modified in the cache based on a writing policy that keeps a number of the memory blocks that are modified at or below a number threshold while maintaining the memory block in the cache. | 01-16-2014 |
20140032818 | PROVIDING A HYBRID MEMORY - A hybrid memory has a volatile memory and a non-volatile memory. The volatile memory is dynamically configurable to have a first portion that is part of a memory partition, and a second portion that provides a cache for the non-volatile memory. | 01-30-2014 |
20140040528 | RECONFIGURABLE CROSSBAR NETWORKS - Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region. | 02-06-2014 |
20140122807 | MEMORY ADDRESS TRANSLATIONS - Memory address translations are disclosed. An example memory controller includes an address translator to translate an intermediate memory address into a hardware memory address based on a function, the address translator to select the function based on at least a portion of the intermediate memory address, the intermediate memory address being identified by a processor. The example memory controller includes a cache to store the function in association with an address range of the intermediate memory sector, the intermediate memory address being within the intermediate memory sector. Further, the example memory controller includes a memory accesser to access a memory module at the hardware memory address. | 05-01-2014 |
20140157054 | MEMORY ERROR IDENTIFICATION BASED ON CORRUPTED SYMBOL PATTERNS - A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern. | 06-05-2014 |
20140325160 | CACHING CIRCUIT WITH PREDETERMINED HASH TABLE ARRANGEMENT - Disclosed herein are an apparatus, an integrated circuit, and method to cache objects. At least one hash table of a circuit comprises a predetermined arrangement that maximizes cache memory space and minimizes a number of cache memory transactions. The circuit handles requests by a remote device to obtain or cache an object. | 10-30-2014 |
20140351495 | LOCAL CHECKPOINTING USING A MULTI-LEVEL CELL - Local checkpointing using a multi-level call is described herein. An example method includes storing a first datum in a first level of a multi-level cell. A second datum is stored in a second level of the multi-level cell, the second datum representing a checkpoint of the first datum. The first datum is copied from the first level to the second level of the multi-level cell to create the checkpoint. | 11-27-2014 |
20140351518 | MULTI-LEVEL CACHE TRACKING TABLE - Disclosed herein are a computing system, integrated circuit, and method to enhance retrieval of cached data. A tracking table is used to initiate a search for data from a location specified in the table, if the data is not in a first level of a multi-level cache hierarchy. | 11-27-2014 |
20150074250 | NETWORK MANAGEMENT - A system and method for network management are described herein. The system includes a number of servers and a first network coupling the servers to each other and configured to connect the servers to one or more client computing devices. The system also includes a second network coupling the servers to each other, wherein data transferred between the servers is transferred though the second network. Network management requests for configuring the second network are communicated to the servers through the first network. | 03-12-2015 |
20150074456 | VERSIONED MEMORIES USING A MULTI-LEVEL CELL - Versioned memories using a multi-level cell (MLC) are disclosed. An example method includes comparing a global memory version to a block memory version, the global memory version corresponding to a plurality of memory blocks, the block memory version corresponding to one of the plurality of memory blocks. The example method includes determining, based on the comparison, which level in a multi-level cell of the one of the plurality of memory blocks stores checkpoint data. | 03-12-2015 |