Patent application number | Description | Published |
20120102273 | MEMORY AGENT TO ACCESS MEMORY BLADE AS PART OF THE CACHE COHERENCY DOMAIN - A system and method is shown wherein a memory agent module to identify a memory command related to virtual memory pages associated with a memory blade and maintain and optimize cache coherency for such pages. The system and method also includes a memory module, operatively connected to the memory agent that includes a page cache used by the memory agent to manage the virtual memory page. Further, the system and method includes a transmission module to transmit the memory command to the memory blade, as well as data structures to facilitate the page migration between the compute blade's local memory and remote memory on the memory blade. | 04-26-2012 |
20150193158 | SMART MEMORY BUFFERS - An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node. | 07-09-2015 |
20150350381 | Vertically-Tiered Client-Server Architecture - Systems and methods of vertically aggregating tiered servers in a data center are disclosed. An example method includes partitioning a plurality of servers in the data center to form an array of aggregated end points (AEPs). Multiple servers within each AEP are connected by an intra-AEP network fabric and different AEPs are connected by an inter-AEP network. Each AEP has one or multiple central hub servers acting as end-points on the inter-AEP network. The method includes resolving a target server identification (ID). If the target server ID is the central hub server in the first AEP, the request is handled in the first AEP. If the target server ID is another server local to the first AEP, the request is redirected over the intra-AEP fabric. If the target server ID is a server in a second AEP, the request is transferred to the second AEP. | 12-03-2015 |
20160034528 | CO-PROCESSOR-BASED ARRAY-ORIENTED DATABASE PROCESSING - A technique includes receiving a user input in an array-oriented database. The user input indicates a database operation and processing a plurality of chunks of data stored by the database to perform the operation. The processing in dudes selectively distributing the processing of the plurality of chunks between a first group of at least one central processing unit and a second group of at least one co-processor. | 02-04-2016 |
20160062821 | INVOKING AN ERROR HANDLER TO HANDLE AN UNCORRECTABLE ERROR - A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state. | 03-03-2016 |
20160077922 | Advanced Versioned Memory - According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored. | 03-17-2016 |
20160078930 | REPRESENTING DATA USING A GROUP OF MULTILEVEL MEMORY CELLS - A memory device includes a group or block of k-level memory cells, where k>2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels. | 03-17-2016 |
20160117196 | LOG ANALYSIS - Log analysis can include transferring compiled log analysis code, executing log analysis code, and performing a log analysis on the executed log analysis code. | 04-28-2016 |