Patent application number | Description | Published |
20100009487 | ONO Spacer Etch Process to Reduce Dark Current - A method of forming a CMOS image sensor device. The method includes providing a semiconductor substrate having a P-type impurity characteristic. The semiconductor substrate includes a surface region. The method includes forming a gate oxide layer overlying the surface region and forming a first gate structure overlying a first portion of the gate oxide layer, the first gate structure has a top surface region and at least a side region. The method forms an N-type impurity region in a portion of the semiconductor substrate to form a photodiode device region from the N-type impurity region and the P-type impurity. The method includes forming a blanket spacer layer including an oxide on nitride on oxide structure overlying at least the first gate structure; and forming one or more spacer structures using the blanket spacer layer for the first gate structure while maintaining a portion of the oxide layer from the oxide on nitride on oxide overlying at least the photo-diode device region | 01-14-2010 |
20100015745 | METHOD AND STRUCTURE FOR A CMOS IMAGE SENSOR USING A TRIPLE GATE PROCESS - A method of forming a CMOS image sensor device, the method includes providing a semiconductor substrate having a P-type impurity characteristic including a surface region. The method form a first thickness of silicon dioxide in a first region of the surface region, a second thickness of silicon dioxide in a second region of the surface region, and a third thickness of silicon dioxide in a third region of the surface region. The method includes forming a first gate layer overlying the second region and a second gate layer overlying the third region, while exposing a portion of the first thickness of silicon dioxide. An N-type impurity characteristic is formed within a region within a vicinity underlying the first thickness of silicon dioxide in the first region of the surface region to cause formation of a photo diode device characterized by the N-type impurity region and the P-type substrate. | 01-21-2010 |
20100136737 | METHOD OF MAKING CMOS IMAGE SENSOR-HYBRID SILICIDE - Techniques for manufacturing a CMOS image sensor are provided. A semiconductor substrate is provided, and at least one isolation region can be formed between a periphery region of the substrate and a photo-sensing region of the substrate. A first well in the periphery region and a second well in the photo-sensing region of the substrate are formed. A third well associated with a photodiode is also formed. A gate oxide layer, polysilicon layer, and first metal layer are respectively deposited. The polysilicon layer and first metal layer are etched to form an least one gate in the photo-sensing region and at least one gate in the periphery region. At least two doped regions in the first well are formed, as well as a doped region in the second well. A silicide block layer is deposited over the photo-sensing region of the substrate. A second metal layer is deposited at least over the periphery region after deposition of the silicide block. The substrate is exposed to a thermal environment to form silicide. The second metal layer is removed by etching. | 06-03-2010 |
20100197066 | METHOD OF INTERCONNECT FOR IMAGE SENSOR - A method for fabricating CMOS image sensor device, the method includes providing a semiconductor substrate having a P type impurity characteristic. The semiconductor substrate includes a surface region. The method forms a first dielectric layer having a first thickness overlying a first region of the semiconductor substrate. The method includes providing a N type impurity region in a portion of the semiconductor substrate underneath the first dielectric layer to cause formation of a photodiode device region characterized by at least the N type impurity region and the P type substrate. A second dielectric layer having a second thickness is formed in a second region of the surface region. The second dielectric layer is formed within a portion of the first region within the first thickness of the first dielectric layer. The method forms a polysilicon gate layer overlying at least the second region to form a contact member coupled to the second region. | 08-05-2010 |
20100253295 | SINGLE-PHASE AND THREE-PHASE DUAL BUCK-BOOST/BUCK POWER FACTOR CORRECTION CIRCUITS AND CONTROLLING METHOD THEREOF - The configurations of a single-phase dual buck-boost/buck power factor correction (PFC) circuit and a controlling method thereof are provided in the present invention. The proposed circuit includes a single-phase three-level buck-boost PFC circuit receiving an input voltage and having a first output terminal, a neutral-point and a second output terminal for outputting a first and a second output voltages, a single-phase three-level buck PFC circuit receiving the input voltage and coupled to the first output terminal, the neutral-point and the second output terminal, a first output capacitor coupled to the first output terminal and the neutral-point, a second output capacitor coupled to the neutral-point and the second output terminal, and a neutral line coupled to the neutral-point. | 10-07-2010 |
20110187909 | METHOD AND SYSTEM FOR CMOS IMAGE SENSING DEVICE - Method and system for manufacturing CMOS image sensing device with reduced blooming. The method includes a step for providing a substrate material. The substrate material can be characterized by a first dimension and a second dimension. In addition, the method includes a step for defining an active region on the substrate material. The active region is characterized by a third dimension and a fourth dimension. The method further includes a step for defining a non-active region on the substrate material. The non-active region is different from the active region. The non-active region is characterized by a fifth dimension and a sixth dimension, the non-active region including a silicon material. The method includes a step for defining a depletion region within the active region. In addition, the method includes a step for forming an n-type region positioned above the depletion region. | 08-04-2011 |
20110204425 | METHOD AND DEVICE FOR CMOS IMAGE SENSING WITH MULTIPLE GATE OXIDE THICKNESSES - A method and device for image sensing. The method includes forming a first well and a second well in a substrate, forming a gate oxide layer with at least a first part and a second part on the substrate, and depositing a first gate region and a second gate region on the gate oxide layer. The first part of the gate oxide layer is associated with a first thickness, and the second part of the gate oxide layer is associated with a second thickness. The first thickness and the second thickness are different. The first gate region is located on the first part of the gate oxide layer associated with the first thickness, while the second gate region is located on both the first part of the gate oxide layer associated with the first thickness and the second part of the gate oxide layer associated with the second thickness. The first gate region is associated with the first well, and the second gate region is associated with the second well. Additionally, the method includes forming a third well in the substrate, implanting a first plurality of ions to form a first lightly doped source region and a first lightly doped drain region in the first well, implanting a second plurality of ions to form at least a second lightly doped drain region in the second well, and implanting a third plurality of ions to form a source in the second well. | 08-25-2011 |
20120012960 | METHOD AND SYSTEM OF EMBEDDED MICROLENS - A method of making an embedded microlens includes providing a substrate having a photo-sensing region, forming a dielectric film overlying the substrate, forming a mask having a circular opening over the dielectric film, the opening being center-aligned over the photo-sensing region, and etching the dielectric film to form a cavity under the mask by introducing an isotropic etchant through the opening, the cavity being characterized by a truncated plano-convex shape having a flat circular bottom and curved peripheral sides convex towards the dielectric film. The method further includes removing the mask, depositing a lens material with a higher refractive index than that of the dielectric film to fill the cavity, planarizing the lens material to form the embedded microlens in the cavity having a smooth top surface, and forming a color filter layer overlying the microlens. The dielectric film includes silicon dioxide having a refractive index of 1.5 or less. | 01-19-2012 |