| Patent application number | Description | Published |
|---|
| 20090001424 | III-nitride power device - A III-nitride power device that includes a Schottky electrode surrounding one of the power electrodes of the device. | 01-01-2009 |
| 20090189187 | Active area shaping for Ill-nitride device and process for its manufacture - A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. | 07-30-2009 |
| 20090278198 | Deep source electrode MOSFET - A power semiconductor device that includes a plurality of source trenches that extend to a depth below the gate electrodes and a termination region that includes a termination trench that is as deep as the source trenches. | 11-12-2009 |
| 20100006895 | III-NITRIDE SEMICONDUCTOR DEVICE - A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and a gate electrode that does not overlap the top surface of the field dielectric bodies and is disposed over a well in the III-nitride heterojunction. | 01-14-2010 |
| 20100258841 | BACK DIFFUSION SUPPRESSION STRUCTURES - An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer. | 10-14-2010 |
| 20100258842 | ENHANCEMENT MODE GALLIUM NITRIDE TRANSISTOR WITH IMPROVED GATE CHARACTERISTICS - An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å. | 10-14-2010 |
| 20100258843 | ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME - An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process. | 10-14-2010 |
| 20100258844 | BUMPED, SELF-ISOLATED GaN TRANSISTOR CHIP WITH ELECTRICALLY ISOLATED BACK SURFACE - A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device. | 10-14-2010 |
| 20100258848 | COMPENSATED GATE MISFET AND METHOD FOR FABRICATING THE SAME - A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer. | 10-14-2010 |
