| Patent application number | Description | Published |
|---|
| 20080203519 | MICROELECTRONIC ASSEMBLY WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE AND A METHOD FOR FORMING THE SAME - A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices ( | 08-28-2008 |
| 20080224221 | CASCODE CURRENT MIRROR AND METHOD - A cascode amplifier (CA) ( | 09-18-2008 |
| 20080224237 | SEMICONDUCTOR DEVICES - An embodiment of a semiconductor device includes a gate electrode overlying a substrate and a lightly doped epitaxial layer formed on the substrate. A high energy implant region forms a well in a source side of the lightly doped epitaxial layer. A self-aligned halo implant region is formed on a source side of the device and within the high energy well implant. An implant region on a drain side of the lightly doped epitaxial layer forms a gate overlapped LDD (GOLD). A doped region within the halo implant region forms a source. A doped region within the gate overlapped LDD (GOLD) forms a drain. | 09-18-2008 |
| 20080277756 | ELECTRONIC DEVICE AND METHOD FOR OPERATING A MEMORY CIRCUIT - An electronic device is disclosed having a dielectric layer ( | 11-13-2008 |
| 20090244928 | DUAL GATE LATERAL DIFFUSED MOS TRANSISTOR - A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions. | 10-01-2009 |
| 20090294849 | RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING - Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices ( | 12-03-2009 |
| 20090315145 | ADJUSTABLE BIPOLAR TRANSISTORS FORMED USING A CMOS PROCESS - By providing a novel bipolar device design implementation, a standard CMOS process ( | 12-24-2009 |
| 20100025765 | DUAL GATE LDMOS DEVICES - An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg | 02-04-2010 |
| 20100156388 | CASCODE CURRENT MIRROR AND METHOD - Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage. | 06-24-2010 |
| 20100164056 | MICROELECTRONIC ASSEMBLIES WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE - Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions. | 07-01-2010 |
| 20100187577 | SCHOTTKY DIODE - Improved Schottky diodes ( | 07-29-2010 |
| 20100213570 | ANTIFUSE - An antifuse ( | 08-26-2010 |
| 20100301400 | SCHOTTKY DIODE - Improved Schottky diodes ( | 12-02-2010 |
| 20100301403 | SEMICONDUCTOR DEVICE WITH MULTIPLE GATES AND DOPED REGIONS AND METHOD OF FORMING - A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate. | 12-02-2010 |
| 20110012232 | BIPOLAR TRANSISTOR - An improved device ( | 01-20-2011 |
| 20110089500 | MULTI-GATE SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions. | 04-21-2011 |
| 20110121428 | HIGH GAIN TUNABLE BIPOLAR TRANSISTOR - An improved bipolar transistor ( | 05-26-2011 |
| 20110147893 | BIPOLAR TRANSISTORS WITH HUMP REGIONS - By providing a novel bipolar device design implementation, a standard CMOS process can be used unchanged to fabricate useful bipolar transistors and other bipolar devices having adjustable properties by partially blocking the P or N well doping used for the transistor base. This provides a hump-shaped base region with an adjustable base width, thereby achieving, for example, higher gain than can be obtained with the unmodified CMOS process alone. By further partially blocking the source/drain doping step used to form the emitter of the bipolar transistor, the emitter shape and effective base width can be further varied to provide additional control over the bipolar device properties. The embodiments thus include prescribed modifications to the masks associated with the bipolar device that are configured to obtain desired device properties. The CMOS process steps and flow are otherwise unaltered and no additional process steps are required. | 06-23-2011 |
