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Jian-Liang
Jian-Liang Chen, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090244948 | EMBEDDED MEMORY APPARATUS WITH REDUCED POWER RING AREA - An embedded memory apparatus with reduced power ring area is disclosed. In order to save the area consumption of a chip, a scheme for removing the power rings originally disposed in a memory core, or another scheme for sharing the power rings with other adjacent memory cores is provided. According to the preferred embodiment of the routing, the power strips originally bridging the inner elements and the outer power serve as the power source (VDD) and ground (VSS) respectively since the peripheral power ring surrounded the core is removed. Thus the area consumption is reduced as if the surrounded power ring shrinks inwardly. The shared power ring for the adjacent memory cores can also be another aspect for reducing the area. | 10-01-2009 |
| 20100050140 | Layout Method for a Chip - A layout method is provided, adaptable to place cell on a chip. Firstly, a chip area is assigned for a floor plan. A global reservation deployment process is then performed to define a plurality of room units to be uniformly distributed on the chip area. Cells are placed on the chip based on the floor plan. The chip area is categorized into at least a high frequency region and a low frequency region according to operation frequencies of the placed cells thereon. A frequency based reservation deployment process is then performed to move one or more room units distributed in the low frequency region toward the high frequency region. A local cell replacement process, a routing and timing analysis are performed. If hotspots are induced, room units around the hotspots are redistributed, and then the steps of local cell replacement, routing and timing analysis are repeated. | 02-25-2010 |
Jian-Liang Chen, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120089754 | HYBRID SERIAL PERIPHERAL INTERFACE DATA TRANSMISSION ARCHITECTURE AND METHOD OF THE SAME - A hybrid serial peripheral interface (SPI) data transmission architecture adapted in a network device for connecting a host and a network is provided. The architecture comprises a RX buffer and RX SPI for maintaining a data receiving process, a TX buffer and TX SPI for maintaining a data transmission process, a configuration and status register and a hybrid SPI processing module. The hybrid SPI processing module makes the RX SPI performs the data transmission process as well when the RX SPI idles and the data transmission process proceeds at the same time and makes the TX SPI to performs the data receiving process as well when the TX SPI idles and the data receiving process proceeds at the same time. A hybrid SPI data transmission method is disclosed herein as well. | 04-12-2012 |
Jian-Liang Lin, Su'Ao Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110176612 | Motion Prediction Method - The invention provides a motion prediction method. First, a plurality of candidate units corresponding to a current unit of a current frame is determined A plurality of motion vectors of the candidate units is then obtained. A plurality of temporal scaling factors of the candidate units is then calculated according to a plurality of temporal distances between a plurality of reference frames of the motion vectors and the current frame. The motion vectors of the candidate units are then scaled according to the temporal scaling factors to obtain a plurality of scaled motion vectors. Finally, a motion vector predictor for motion prediction of the current unit is then selected from the candidate units according to the scaled motion vectors. | 07-21-2011 |
| 20110176613 | Motion Prediction Method and Video Encoding Method - The invention provides a motion prediction method. First, a plurality of motion vector predictors is obtained to be included in a candidate set for motion prediction of a current unit of a current frame. Whether the current frame is a non-reference frame which is not referred to by other frames for motion prediction is then determined. When the current frame is not the non-reference frame, any motion vector predictor corresponding to a previously coded frame is removed from the candidate set, and a motion vector of the current unit is predicted according to the motion vector predictors of the candidate set. | 07-21-2011 |
Jian-Liang Lin, Yilan TW
| Patent application number | Description | Published |
|---|---|---|
| 20120008688 | Method and Apparatus of Temporal Motion Vector Prediction - An apparatus and method for motion vector prediction for a current block in a picture are disclosed. In video coding systems, the spatial and temporal redundancy is exploited using spatial and temporal prediction to reduce the information to be transmitted. Motion Vector Prediction (MVP) has been used to further conserve the bitrate associated with motion vector. In conventional temporal MVP, the predictor is often based on a single candidate such as the co-located motion vector in the previous frame/picture. If the co-located motion vector in the previous frame/picture does not exist, the predictor for the current block is not available. A technique for improved MVP is disclosed where the MVP utilized multiple candidates based on co-located motion vectors from future and/or past reference pictures. The candidates are arranged according to priority order to provide better availability of MVP and also to provide more accurate prediction. Furthermore, the MVP technique disclosed can be operated in a closed-loop fashion so that no additional side information or minimum additional side information is required. | 01-12-2012 |