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Jian-Hong
Jian-Hong Chen, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100068656 | HIGH ETCH RESISTANT MATERIAL FOR DOUBLE PATTERNING - The present invention includes a lithography method comprising forming a first patterned insist layer including at least one opening therein over a substrate. A water-soluble polymer layer is formed over the first patterned resist layer and the substrate, whereby a reaction occurs at the interface of the first patterned resist layer and the water-soluble polymer layer. The non-reacted water-soluble polymer layer is removed. Thereafter, a second patterned resist layer is formed over the substrate, wherein at least one portion of the second patterned resist layer is disposed within the at least one opening of the first patterned resist layer or abuts at least one portion of the first patterned resist layer. The substrate is thereafter etched using the first and second patterned resist layers as a mask. | 03-18-2010 |
Jian-Hong Chen, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20110026876 | NANO/MICRO-PATTERNED OPTICAL DEVICE AND FABRICATION METHOD THEREOF - A nano/micro-patterned optical device includes a soft film substrate and nano/micro thin wires. A surface of the soft film substrate includes a nano/micro-pattern formed through a lithography process, and the nano/micro-pattern includes a plurality of depressed grooves. The nano/micro thin wires are placed in the depressed grooves, and used to form a plurality of optical waveguides, in which the optical waveguides include at least one optical coupling region, and the optical coupling region is located on a joining position of the optical waveguides. A fabrication method of the nano/micro-patterned optical device is also provided. | 02-03-2011 |
Jian-Hong Chen, Puzih City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090184081 | Temperature-sensing feeding bottle structure - A feeding bottle includes a body, a temperature sensing and measuring plate on a lateral wall portion of the body, and a plate-shaped warning device covered by the temperature sensing and measuring plate; the temperature sensing and measuring plate can change colors with temperature to indicate the temperature for the users such as the parents, nursing persons, and diners; the warning device can give a certain kind of sound effect according to the temperature so that the parents/nursing persons can easily make sure that the food contents of the feeding bottle isn't too hot before they feed little children/persons with disabilities; little children, the elderly, and persons with visual disabilities also can be directly warned by the warning sound effects given by the warning device if the temperature is too high. | 07-23-2009 |
Jian-Hong Chen, Dashu Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110214031 | ERROR CORRECTION DECODER, ERROR CORRECTION VALUE GENERATOR, AND ERROR CORRECTION SYSTEM - An error correction decoder includes a syndrome generator and an error correction value generator. The syndrome generator is operable to generate a plurality of syndromes based upon a received signal generated according to a generator polynomial. The error correction value generator is operable to generate a plurality of product values. Each of the product values is generated for one of the syndromes based upon a respective power of the roots of the generator polynomial. The respective power is determined based upon a respective index corresponding to one of the syndromes to be considered and unit positions of the received signal. The error correction value generator is further operable to generate an error correction value according to the product values, and to provide an error correcting device coupled thereto with the error correction value for correcting an error of the received signal. | 09-01-2011 |
Jian-Hong Chen, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080286682 | MATERIAL AND METHOD FOR PHOTOLITHOGRAPHY - A photosensitive material for use in semiconductor manufacture comprises a copolymer that includes a plurality of photoresist chains and a plurality of hydrophobic chains, each hydrophobic chain attached to the end of one of the photoresist chains. The copolymer in response to externally applied energy will self-assemble to a photoresist layer and a hydrophobic layer. | 11-20-2008 |
| 20090233238 | Double Patterning Strategy For Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist pattern. | 09-17-2009 |
| 20100209852 | TRACK NOZZLE SYSTEM FOR SEMICONDUCTOR FABRICATION - The present disclosure provides a method for fabricating a semiconductor device using a track pipeline system. The method includes storing a plurality of chemicals in a plurality of storage units of the system, wherein each storage unit is operable to store one of the chemicals, mixing the chemicals into a mixture, and dispensing the mixture onto a wafer using a nozzle of the system. | 08-19-2010 |
Jian-Hong Liao, Longtan Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20100136712 | COMPOUND AND METHOD FOR PRODUCING THE SAME - The invention provides a Ti doped lead barium zirconate dielectric material which could be applied to high frequency devices. The material comprises a compound with the chemical formula (Pb | 06-03-2010 |
Jian-Hong Lin, Huwei Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20120002375 | METHOD AND STRUCTURE FOR DISSIPATING HEAT AWAY FROM A RESISTOR HAVING NEIGHBORING DEVICES AND INTERCONNECTS - A semiconductor structure for dissipating heat away from a resistor having neighboring devices and interconnects. The semiconductor structure includes a semiconductor substrate, a resistor disposed above the semiconductor substrate, and a thermal protection structure disposed above the resistor. The thermal protection structure has a plurality of heat dissipating elements, the heat dissipating elements having one end disposed in thermal conductive contact with the thermal protection structure and the other end in thermal conductive contact with the semiconductor substrate. The thermal protection structure receives the heat generated from the resistor and the heat dissipating elements dissipates the heat to the semiconductor substrate. | 01-05-2012 |
Jian-Hong Lin, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110025590 | DISPLAY DEVICE HAVING BI-DIRECTIONAL SCAN MECHANISM AND GATE SIGNAL SCANNING METHOD THEREOF - A display device having bi-directional scan mechanism includes a plurality of gate lines, a first shift register circuit and a second shift register circuit. The first shift register circuit includes a plurality of forward shift register stages. The second shift register circuit includes a plurality of backward shift register stages. Each of the gate lines is electrically connected to both a corresponding forward shift register stage and a corresponding backward shift register stage. When the first shift register circuit is enabled, the forward shift register stages are employed to provide plural forward gate signals sequentially enabled for scanning the gate lines based on a first sequence. When the second shift register circuit is enabled, the backward shift register stages are employed to provide plural backward gate signals sequentially enabled for scanning the gate lines based on a second sequence opposite to the first sequence. | 02-03-2011 |
Jian-Hong Lin, Yunlin TW
| Patent application number | Description | Published |
|---|---|---|
| 20080251923 | Seal ring structures with reduced moisture-induced reliability degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 10-16-2008 |
| 20090058434 | METHOD FOR MEASURING A PROPERTY OF INTERCONNECTIONS AND STRUCTURE FOR THE SAME - A method for measuring a property of interconnections is provided. The method includes the following steps. A plurality of interconnection test patterns are provided. A pad to which the plurality of interconnection test patterns are parallelly connected is formed. At least one resistor is formed between at least one of the plurality of interconnection test patterns and the pad. The property of the plurality of interconnection test patterns is measured by applying a current, a voltage and/or a mechanical stress to the pad. | 03-05-2009 |
| 20100271753 | METAL OXIDE METAL CAPACITOR WITH SLOT VIAS - A capacitor includes the first electrode comprising the first conductive lines and vias, where the first conductive lines on the same layer are parallel to each other and connected to the first periphery conductive line, and the first conductor lines aligned in adjacent layers are coupled to each other by the vias; the second electrode aligned opposite to the first electrode comprising the second conductive lines and vias, where the second conductive lines on the same layer are parallel to each other and connected to the second periphery conductive line, and the second conductor lines aligned in adjacent layers are coupled to each other by the vias; and oxide layers formed between the first electrode and the second electrode, where the vias have rectangular (slot) shape on a layout. In one embodiment, the conductive lines and vias are metal, e.g. copper, aluminum, or tungsten. The vias can have various sizes. | 10-28-2010 |
| 20100327456 | Process for Improving the Reliability of Interconnect Structures and Resulting Structure - An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate. | 12-30-2010 |
| 20110108945 | Seal Ring Structures with Reduced Moisture-Induced Reliability Degradation - A semiconductor chip includes a seal ring adjacent to edges of the semiconductor chip; an opening extending from a top surface to a bottom surface of the seal ring, wherein the opening has a first end on an outer side of the seal ring and a second end on an inner side of the seal ring; and a moisture barrier having a sidewall parallel to a nearest side of the seal ring, wherein the moisture barrier is adjacent the seal ring and has a portion facing the opening. | 05-12-2011 |
Jian-Hong Lin, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100014030 | ARRAY SUBSTRATE AND DISPLAY PANEL THEREOF - An array substrate having a display region and a peripheral circuit region adjacent to the display region is provided. The array substrate includes a pixel array, a plurality of test shorting bars and a plurality of wires. The pixel array is disposed in the display region. The test shorting bars are disposed in the peripheral circuit region. The wires electrically connected with the pixel array are disposed in the peripheral circuit region. Specially, at least one wire and the test shorting bar share a part for connecting each other and the part forms a common trace. | 01-21-2010 |
Jian-Hong Lin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110069806 | PULL-DOWN CONTROL CIRCUIT AND SHIFT REGISTER OF USING SAME - The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T | 03-24-2011 |