Patent application number | Description | Published |
20100318721 | PROGRAM FAILURE HANDLING IN NONVOLATILE MEMORY - In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array. | 12-16-2010 |
20110096601 | Non-Volatile Memory And Method With Accelerated Post-Write Read To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC and estimated to represent a worst error rate among the copy it is sampling. One embodiment has the sample taken from one bit of each multi-bit memory cell of a group. | 04-28-2011 |
20110099418 | Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used. | 04-28-2011 |
20110099460 | Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced. | 04-28-2011 |
20110154158 | SYSTEM AND METHOD OF ERROR CORRECTION OF CONTROL DATA AT A MEMORY DEVICE - A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion. | 06-23-2011 |
20120272120 | Non-Volatile Memory and Method with Post-Write Read and Adaptive Re-Write to Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. For acceptable quality assurance, conventional error correction codes (“ECC”) have to correct a maximum number of error bits up to the far tail end of a statistical population. The present memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. If excessive error bits (at the far tail-end) occur after writing a group of data to the second portion, the data is adaptively rewritten to the first portion which will produce less error bits. Preferably, the data is initially written to a cache also in the first portion to provide source data for any rewrites. Thus, a more efficient ECC not requiring to correcting for the far tail end can be used. | 10-25-2012 |
20130170301 | Wordline-to-Wordline Stress Configuration - A method and system for performing wordline-to-wordline stress routines on a storage device is disclosed. Stress routines may be performed to reduce state widening in multi-level memory cells in the storage device. However, data retention problems may result if the stress routines are performed too often. In order to perform the stress routines at the proper times, a stress control variable is used. The stress control variable may be indicative of age of the storage device (such as the number of erase cycles performed on a memory block in the storage device). The stress control variable is input to a look-up table (or other logical construct), with the output of the look-up table indicating whether to perform the wordline-to-wordline stress routine. In this way, the stress routines may be performed to reduce state widening while reducing the ill effects of data retention. | 07-04-2013 |
20130173844 | SLC-MLC Wear Balancing - A method and system for SLC-MLC Wear Balancing in a flash memory device is disclosed. The flash memory device includes a single level cell (SLC) portion and a multi-level cell (MLC) portion. The age of the SLC portion and the MLC portion may differ, leading potentially to one portion wearing out before the other. In order to avoid this, a controller is configured to receive an age indicator from one or both of the SLC portion and the MLC portion, determine, based on the age indicator, whether to modify operation of the SLC portion and/or the MLC portion, and in response to determining to modifying operation, modify the operation of the at least one of the SLC portion or the MLC portion. The modification of the operation may thus balance wear between the SLC and MLC portions, thereby potentially extending the life of the flash memory device. | 07-04-2013 |
20130346805 | FLASH MEMORY WITH TARGETED READ SCRUB ALGORITHM - A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation. | 12-26-2013 |
20140355344 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 12-04-2014 |
20140355345 | Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit. | 12-04-2014 |
20140359398 | Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block. | 12-04-2014 |
20140359400 | Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block. | 12-04-2014 |