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Ji, NY
Brain L. Ji, Chappaqua, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110031633 | AIR CHANNEL INTERCONNECTS FOR 3-D INTEGRATION - A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure. | 02-10-2011 |
Brian L. Ji, Chappaqua, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110018511 | INTEGRATABLE EFFICIENT SWITCHING DOWN CONVERTER - A converter circuit and methods for operating the same. The converter circuit includes a supply voltage, a capacitor, an inductor, and four stacked switching elements. Each switching element is adjustable from a low resistance state to a high resistance state by a control signal. The inductor outputs current to a circuit load. The circuit may be operated in a first mode such that the output is adjustable between the supply voltage and half the supply voltage. Alternatively, in a second mode of operation, the output is adjustable from half the supply voltage to a ground voltage. | 01-27-2011 |
| 20110051482 | CONTENT ADDRESSABLE MEMORY ARRAY PROGRAMMED TO PERFORM LOGIC OPERATIONS - A memory device for performing logical operations on two or more input variables includes a match line and first and second memory cells. The first and second memory cells collectively include a first, second, third and fourth memory element. The first, second, third and fourth memory elements may have either a first value or a second value programmed therein and wherein the first, second, third and fourth memory elements are programmed to either the high or low resistive values based on a particular logic function to be performed. | 03-03-2011 |
| 20110051483 | CONTENT ADDRESSABLE MEMORY ARRAY - A memory device for storing one or more addresses includes a match line and first and second memory cells that form a 2-bit memory cell. Each memory cell includes two memory elements coupled to a match line and selection lines coupled thereto. The selection lines provide a signal representative of a logical combination of at least two different inputs. | 03-03-2011 |
| 20110051485 | CONTENT ADDRESSABLE MEMORY ARRAY WRITING - A memory system for storing one or more addresses includes a transposable memory having word lines, bit lines, transposed word lines and transposed bit lines and that receives and stores an input array having dimensions M by N and a content addressable memory (CAM) that reads the transposed word lines of the transposable memory to form input words and that stores the input words in an N by M array. | 03-03-2011 |
| 20110051486 | CONTENT ADDRESSABLE MEMORY REFERENCE CLOCK - A memory system includes a content addressable memory (CAM) including a plurality of match lines, each match line having a plurality of memory cells coupled thereto. The system also includes a match detector coupled to the CAM and a reference match line having a plurality of reference memory cells coupled thereto, the reference memory cells being of the same type and the memory cells. The system also includes a match line sensor coupled to the reference match line and the match detector that determines a characteristic of the reference match line and provides a timing signal to the match detector based on the characteristic. | 03-03-2011 |
Brian L. Ji, Yorktown Heights, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110108900 | BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR - A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack. | 05-12-2011 |
Chunxin Ji, Penfield, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20100291461 | PREPARATION OF NANOSTRUCTURED THIN CATALYTIC LAYER-BASED ELECTRODE INK - A method of making an electrode ink containing nanostructured catalyst elements is described. The method comprises providing an electrocatalyst decal comprising a carrying substrate having a nanostructured thin catalytic layer thereon, the nanostructure thin catalytic layer comprising nanostructured catalyst elements; providing a transfer substrate with an adhesive thereon; transferring the nanostructured thin catalytic layer from the carrying substrate to the transfer substrate; removing the nanostructured catalyst elements from the transfer substrate; providing an electrode ink solvent; and dispersing the nanostructured catalyst elements in the electrode ink solvent. Electrode inks, coated substrates, and membrane electrode assemblies made from the method are also described. | 11-18-2010 |
| 20100291467 | FABRICATION OF CATALYST COATED DIFFUSION MEDIA LAYERS CONTAINING NANOSTRUCTURED THIN CATALYTIC LAYERS - A method of transferring nanostructured thin catalytic layers to a gas diffusion layer and thus making a catalyst coated diffusion media is described. The method includes treating the gas diffusion layer with a temporary adhesive to temporarily increase the adhesion strength within the microporous layer and to carbon fiber paper substrate, transferring the nanostructured thin catalytic layer to the microporous side of a gas diffusion media layer. The nanostructured thin catalytic layer can then be further processed, including adding additional components or layers to the nanostructured thin catalytic layer on the gas diffusion media layer. Preparation of catalyst coated diffusion media and a catalyst coated diffusion media based membrane electrode assembly (MEA) are also described. | 11-18-2010 |
| 20100291473 | FABRICATION OF ELECTRODES WITH MULTIPLE NANOSTRUCTURED THIN CATALYTIC LAYERS - A method of making a reconstructed electrode having a plurality of nanostructured thin catalytic layers is provided. The method includes combining a donor decal comprising at least one nanostructured thin catalytic layer on a substrate with an acceptor decal comprising a porous substrate and at least one nanostructured thin catalytic layer. The donor decal and acceptor decal are bonded together using a temporary adhesive, and the donor substrate is removed. The temporary adhesive is then removed with appropriate solvents. Catalyst coated proton exchange membranes and catalyst coated diffusion media made from the reconstructed electrode decals having a plurality of nanostructured thin catalytic layers are also described. | 11-18-2010 |
Chunxin Ji, Rochester, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110070524 | Diffusion Media, Fuel Cells, and Fuel Cell Powered Systems - In at least certain embodiments, the present invention provides a diffusion media and fuel cells and systems employing the diffusion media. In at least one embodiment, the diffusion media comprises a porous matrix having an outer surface and a hydrophilic polymeric coating on at least a portion of the porous matrix with the hydrophilic coating comprising the cured product of a formulation comprising a hydrophilic monomer. | 03-24-2011 |
Jiang Ji, Clifton Park, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090242479 | AROMATIC HALOSULFONYL ISOCYANATE COMPOSITIONS - The present invention provides a polymer composition comprising structural units derived from an aromatic halosulfonyl isocyanate having structure I | 10-01-2009 |
| 20090242831 | AROMATIC HALOSULFONYL ISOCYANATE COMPOSITIONS - The present invention provides a monomer composition comprising an aromatic halosulfonyl isocyanate having structure I | 10-01-2009 |
Qun-Sheng Ji, Farmingdale, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080299113 | Combined treatment with and composition of 6,6-bicyclic ring substituted heterobicyclic protein kinase inhibitor and anti-cancer agents - The present invention provides a method for treating tumors or tumor metastases in a patient, comprising administering to the patient simultaneously or sequentially a therapeutically effective amount of an EGFR kinase inhibitor and an IGF1R inhibitor compound of Formula I combination, with or without additional agents or treatments, such as other anti-cancer drugs or radiation therapy. The invention also encompasses a pharmaceutical composition that is comprised of an EGFR kinase inhibitor and IGF1R inhibitor compound of Formula I combination with a pharmaceutically acceptable carrier. The IGF1R inhibitor is represented by Formula I: | 12-04-2008 |