Patent application number | Description | Published |
20080256153 | RANDOM NUMBER SIGNAL GENERATOR USING PULSE OSCILLATOR - A random number signal generator using pulse oscillators, the generator including: a first pulse oscillator oscillating a first pulse at high speed; a second pulse oscillator oscillating a second pulse; a sampler receiving an output pulse of the first oscillator as data, receiving an output pulse of the second pulse oscillator as a clock signal, and outputting a plurality of output signals; and a digital processor generating a random number signal with a desired size by using the output signals of the sampler. | 10-16-2008 |
20090056448 | BIDIRECTIONAL READOUT CIRCUIT FOR DETECTING DIRECTION AND AMPLITUDE OF CAPACITIVE MEMS ACCELEROMETERS - There is provided a bidirectional readout circuit for detecting direction and amplitude of an oscillation sensed at a capacitive microelectromechanical system (MEMS) accelerometer, the bidirectional readout circuit converting capacitance changes of the capacitive MEMS accelerometer into a time change amount by using high resolution capacitance-to-time conversion technology and outputting the time change amount as the direction and the amplitude of the oscillation by using time-to-digital conversion (TDC) technology, thereby detecting not only the amplitude of the oscillation but also the direction thereof, which is capable of being applied to various MEMS sensors. | 03-05-2009 |
20100031052 | LOW POWER HMAC ENCRYPTION APPARATUS - There are provided a low power SHA-1 hash algorithm apparatus having a low power structure and optimized to a trusted platform module (TPM) applied to a mobile trusted computing environment and a low power keyed-hash message authentication code (HMAC) encryption apparatus using the low power SHA-1 hash algorithm apparatus, the HMAC encryption apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector; and a controller controlling operations of the key padder, data connector, and data padder, a sequence of performing a hash algorithm of the SHA-1 hash algorithm part, and storing an operation result to read data required for performing an encryption operation and store data with memory. | 02-04-2010 |
20100066582 | CURRENT MODE DOUBLE-INTEGRATION CONVERSION APPARATUS - A double-integration signal processing apparatus for pulse width amplification and A/D conversion is provided. The current mode double-integration conversion apparatus includes: a current mode double-integration unit which integrates an input current in a predetermined time interval and outputs an integration voltage; a comparison unit which compares the integration voltage output from the current mode double-integration unit with a predetermined comparison voltage V k and outputs an comparison pulse signal; and a gate logic unit which performs a logic operation by using the comparison pulse signal of the comparison unit and an internal signal and outputs an logic operation pulse signal. Accordingly, the current mode double-integration conversion apparatus can be applied to various sensors. | 03-18-2010 |
20100104098 | CRYPTOGRAPHIC METHOD AND DEVICE FOR SCHEDULING AND COMPRESSING MESSAGE BASED ON SECURE HASH ALGORITHM - The present invention relates to a secure hash algorithm (SHA)-based message schedule operation method, a message compression operation method, and a cryptographic device performing the same. The present invention sequentially performs the message schedule operation by using an adder. Also, a memory for storing operation data input for the message schedule operation is used from a 17th round to store intermediate data generated by the message schedule operation. Further, the message compression operation is sequentially performed by using one adder. | 04-29-2010 |
20100146296 | APPARATUS AND METHOD FOR HASH CRYPTOGRAPHY - An apparatus for hash cryptography has a hardware structure that is capable of providing both secure hash algorithm (SHA)-1 hash calculation and SHA-256 hash calculation. The apparatus for hash cryptography generates a plurality of first message data corresponding to a plurality of first rounds when the SHA-1 hash calculation is performed and generates a plurality of second message data corresponding to a plurality of second rounds when the SHA-256 hash calculation is performed by using one memory, one first register, one XOR calculator, and one OR calculator, calculates a message digest by the SHA-1 hash calculation by using the plurality of first message data when the SHA-1 hash calculation is performed, and calculates a message digest by the SHA-256 by using the plurality of second message data when the SHA-256 hash calculation is performed. | 06-10-2010 |
20100171586 | RFID TAG WITH LED AND RF IDENTIFICATION MANAGING METHOD USING THE SAME - A RFID tag having a LED is provided. The RFID tag includes an antenna, a RF processor, a controller, a memory, at least one of LEDs, and a LED switching unit. The RF processor receives and transmits a wireless signal through the antenna, and modulates and demodulates transmitted and received signal and data. The controller analyzes a received data outputted from the RF signal processor and generally controls the RFID tag. The memory stores the received data in response to the controller. The LED switching unit turns on/off at least one of the LEDs in response to the controller. | 07-08-2010 |
20100315194 | SENSOR SIGNAL PROCESSOR APPARATUS - Provided is a sensor signal processor apparatus having good characteristics and providing an easy and simple interface for various sensors. The sensor signal processor apparatus includes a current source, a sensor, a ramp integrator, a comparator, and a controller. The current source generates a constant current according to a preset value, and the sensor outputs a sensor voltage using the current from the current source. The ramp integrator generates and outputs an integral voltage according to an input command, and the comparator compares the sensor voltage of the sensor with the integral voltage of the ramp integrator and outputting a result of the comparison. The controller controls the generating and outputting of the integral voltage of the ramp integrator according to the comparison result of the comparator. | 12-16-2010 |
20110084603 | INORGANIC ELECTROLUMINESCENT DEVICE AND MANUFACTURING METHOD THEREOF - An inorganic electroluminescent device includes: patterned metal electrodes periodically disposed at pre-set intervals; and a phosphor layer positioned on the patterned metal electrodes, wherein as a first voltage and a second voltage are alternately applied to the patterned metal electrodes according to the order of their disposition, light emitted from the phosphor layer is discharged to the spaces between the patterned metal electrodes. | 04-14-2011 |
20110104322 | TEMPLATES USED FOR NANOIMPRINT LITHOGRAPHY AND METHODS FOR FABRICATING THE SAME - Provided are a template used for nanoimprint lithography and a method for fabricating the same. A raised first deposition layer pattern including at least one downwardly sloped side surface is formed on a substrate. A second deposition layer pattern covering the side surface of the raised first deposition layer pattern and progressively decreasing in width downward along the side surface of the raised first deposition layer pattern is formed. A third deposition layer is formed on the entire surface of a structure on which the second deposition layer pattern. A second deposition layer nano pattern between the raised first deposition layer pattern and a planarized third deposition layer is formed by planarizing the third deposition layer to expose upper surfaces of the raised first deposition layer pattern and the second deposition layer pattern. An intaglio nano pattern defined by side surfaces sloped downward from upper surfaces of the raised first deposition layer pattern and the planarized third deposition layer to the surface of the substrate is formed by removing the second deposition layer nano pattern. | 05-05-2011 |
20110136338 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent. | 06-09-2011 |
20110147468 | RFID TAG - Provided is a radio frequency identification (RFID) tag whose data can be stably read at a long distance on the basis of a passive RFID tag. The RFID tag includes a rechargeable unit charged to a predetermined voltage, and a power source including a direct current (DC) power source including a rectifier for converting an RF signal into DC power and a regulator for supplying a predetermined DC voltage, an interceptor disposed between the rechargeable unit and the DC power source to connecting or disconnecting the power to the rechargeable unit, and an overvoltage preventor connected to an output terminal of the DC power source in parallel. | 06-23-2011 |
20110147787 | ORGANIC LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - An organic light emitting diode (OLED) and a method for manufacturing the same are provided. In the OLED, patterned metal electrodes are positioned on one or more of upper and lower portions of a light emission layer to allow light generated from the light emission layer to emit to an area between the patterned metal electrodes. | 06-23-2011 |
20120086132 | METHOD OF MANUFACTURING VIA ELECTRODE - Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles. | 04-12-2012 |
20120137907 | INTAGLIO PRINTING PLATE INCLUDING SUPPLEMENTARY PATTERN AND METHOD FOR FABRICATING THE SAME - Disclosed is an intaglio printing plate including: a pattern portion where a to-be-printed pattern is located; a non-pattern portion corresponding to a remaining area other than the pattern portion; and a supplementary pattern portion having a repetitive pattern with a predetermined form, wherein at least a part of the pattern portion is divided by a pattern structure that is formed by the supplementary pattern portion. | 06-07-2012 |
20120140350 | PRINTING PLATE AND MIRROR THEREOF - Disclosed are a printing plate and a mirror thereof, the printing plate including: printing portions for transferring an immersed solution, the printing portions being formed flat and arranged at regular intervals on one side of an upper part of the printing plate; and non-printing portions corresponding to a remaining area other than the printing portions, the non-printing portions being formed with at least two concavities and convexities respectively and arranged at regular intervals on the other side of the upper part of the printing plate. | 06-07-2012 |
20120161941 | RFID TAG - An RFID tag includes: an antenna receiving an RF signal from a reader; an AFE (analog front end) generating voltage using the RF signal; and one or more switches interposed between the antenna and the AFE and controlling the connection between the antenna and the AFE through the switch operation. | 06-28-2012 |
20140138432 | SENSOR TAG AND METHOD OF PROVIDING SERVICE USING THE SAME - A sensor tag includes: a tag chip that receives a supply of a driving voltage that is generated from a radio frequency (RF) signal that is received from a reader and that transmits sensor data to the reader according to a request from the reader; at least one sensor that receives a supply of a necessary driving voltage from the tag chip and that measures corresponding sensor data; and a micro controller unit (MCU) that receives a supply of a necessary driving voltage from the tag chip and that transfers sensor data that is measured from the at least one sensor to the tag chip. | 05-22-2014 |
20140159875 | TERMINAL AND OPERATION CONTROL METHOD THEREOF - A terminal and an operation control method thereof are disclosed. A terminal performs an authentication procedure upon receiving a tag device's information from the tag device. If the tag device is identified as a registered tag device in the authentication procedure, initial data corresponding to a function to control the terminal even in a power-saving mode or a lock mode is received from the tag device, and the function corresponding to the initial data is performed. | 06-12-2014 |
20140327390 | APPARATUS AND METHOD FOR WIRELESS CHARGING - A wireless charging apparatus is provided. The wireless charging apparatus includes: an antenna that receives electrical waves; at least two charging power generators that generate charging power for charging a battery using the electrical waves received through the antenna; and a controller that senses a frequency of the electrical waves received through the antenna and that activates one of the at least two charging power generators according to a sensed result. | 11-06-2014 |
20140354460 | PULSE GENERATOR AND ANALOG-DIGITAL CONVERTER INCLUDING THE SAME - Provided is a pulse generator. The pulse generator includes: a pulse generation unit receiving an analog signal and generating a first pulse signal in response to a comparison result of a voltage level applied to a first node and a reference voltage according to the received analog signal; a pulse amplification unit generating a second pulse signal having a wider pulse width than the first pulse signal according to a comparison result of a voltage level applied to a second node and a ground voltage, in response to the first pulse signal; and a gate logic outputting a final pulse signal as a signal for digital conversion by performing a logic operation on the first and second pulse signals. | 12-04-2014 |