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Ji-Hyun
Ji Hyun Jung, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110282546 | APPARATUS AND METHOD FOR IDENTIFYING TIRE PRESSURE SENSOR MODULE - Disclosed are an apparatus and a method for identifying a plurality of tire pressure sensor modules. Data wirelessly transmitted from the tire pressure sensor modules are received by using a signal cable connected between a wheel speed sensor module and a control module. The control module identifies the pressure sensor modules mounted on vehicle tires according to the intensities of received signals. | 11-17-2011 |
Ji Hyun Lee, Nonsan KR
| Patent application number | Description | Published |
|---|---|---|
| 20110144348 | VOLTAGE-SENSITIVE DYE AND METHOD OF PREPARING THE SAME - Provided is a voltage sensitive dye represented by Formula 7. | 06-16-2011 |
Ji Hyun Lee, Jeonju KR
| Patent application number | Description | Published |
|---|---|---|
| 20120129258 | CELL CHIP AND METHOD OF FABRICATING THE SAME - Disclosed herein are a cell chip and a method of fabricating the same. The cell chip includes a cell-adhesivecell-adhesive layer disposed on a substrate. Photocrosslinked polymer barriers are disposed on the cell-adhesivecell-adhesive layer. The photocrosslinked polymer barriers may serve to restrict and grow cells only on the cell-adhesivecell-adhesive layer exposed between the barriers. Therefore, a cell growth direction may be precisely controlled. In addition, the photocrosslinked polymer barrier has a pattern formed by light, and simplifies a process of fabricating a cell chip. | 05-24-2012 |
Ji Hyun Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120108255 | APPARATUS FOR TRANSMITTING A SIGNAL USING SCHEDULING INFORMATION IN A MOBILE COMMUNICATION SYSTEM AND METHOD FOR SAME - Disclosed are a method for transmitting scheduling information in a mobile communication system and a femtocell base station using the method. A femtocell base station transmits scheduling information using a layered scheduling system in which the femtocell base station receives an allocated resource from a macrocell base station, and allocates the resource to femtocell users within a resource region thereof. | 05-03-2012 |
Ji Hyun Lim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090262714 | Network gateway and network system for a vehicle - The present invention relates to the network gateway for a vehicle and network system in which the mobile device which supports the wireless LAN is able to use the Internet by using the telematics module of a vehicle. For this, the present invention includes an user interface in which a user command is inputted and the process result for the user command is indicated; a telematics module in which a mobile communications network connecter is mounted to be able be connected to Internet that the mobile communications network provides; a mobile device equipped with a wireless LAN; and a network gateway which connects the mobile device to the Internet through the telematics module according to the request of the user interface or the mobile device in the state of being connected to the mobile device through the wireless LAN. | 10-22-2009 |
| 20090265633 | Network gateway for a vehicle - The present invention relates to the network gateway for the vehicle sharing the contents between all display units of an inside-vehicle. For this, the invention includes an interface connecter which is connected respectively to at least one or more display units that receive a user command and display the process result for the user command; and a controller which shares a contents by transmitting the contents from a specific display unit to another display unit in case it is commanded to perform the contents sharing from the specific display unit through the interface connecter. | 10-22-2009 |
Ji Hyun Lim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090013185 | COMPATIBLE SYSTEM OF DIGITAL RIGHTS MANAGEMENT AND METHOD FOR OPERATING THE SAME - Disclosed is a compatible system of digital rights management which enables the reproduction of the same contents between apparatuses each employing a different digital rights management system. The compatible system of digital rights management comprises: a user server including a first authentication document of a first apparatus; a second apparatus connected to the first apparatus and outputting a contents request signal and a second authentication document to reproduce substantially the same contents; and a provider server forming a virtual safe channel with the user server based on the contents request signal to receive the first authentication document, and generating first and second licenses encrypted through the first and second authentication documents to transmit the same to the second apparatus. | 01-08-2009 |
| 20090044008 | DRM SYSTEM AND METHOD OF MANAGING DRM CONTENT - The present invention relate to a DRM system and a method of managing DRM content, which allow the user of content protected by DRM to use DRM content even through an unconnected device, which is not connected to a network. The DRM system includes a DRM server for issuing a Public Key Infrastructure (PKI)-based certificate and a key pair to an unconnected device via a network client connected to the unconnected device so as to allow the unconnected device to share a right to DRM content with the network client and to authenticate the unconnected device and permit the unconnected device to join a domain on a basis of the certificate and the key pair via the network client. | 02-12-2009 |
| 20090044278 | METHOD OF TRANSMITTING DRM CONTENT - Disclosed herein is a method of transmitting DRM content, stored in a device, to another external device. A rights object is embedded in a mutable information box of a Digital rights management Content Format (DCF), thus integrating the rights object and the DCF into a single object. The DCF, in which the rights object is embedded, is transmitted with a message authentication code. The message authentication code is embedded in the mutable information box of the DCF so as to enable integrity validation for the DCF, in which the rights object is embedded. The rights object is a domain rights object capable of being shared by one or more devices. The DCF, in which the rights object is embedded, is transmitted to the external device via mobile storage in which no security function exists or no security function is set. | 02-12-2009 |
Ji Hyun Min, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080210899 | Magnetic Core - Ceramic Shell Nanocrystals and Manufacturing Method Thereof - Provided are magnetic core-ceramic shell (e.g., magnetite (Fe | 09-04-2008 |
| 20090155617 | IRON-GOLD BARCODE NANOWIRE AND MANUFACTURING METHOD THEREOF - Disclosed are an Fe—Au barcode type nanowire and a method of manufacturing the same. The nanowire has a magnetic-optical multifunction and is suitable for adjusting magnetic intensity thereof. The Fe—Au nanowire has a multilayered structure, in which an iron layer and a gold layer are alternately and repeatedly formed, and is formed in a single plating bath through a pulse electro-deposition. | 06-18-2009 |
| 20100163419 | METHOD FOR FABRICATING MULTI-COMPONENT NANOWIRES - A method for fabricating multi-component nanowires is disclosed, which can make multi-component nanowires used to realize a nanowire-based memory device by an electroplating process using a multi-component solution. The method for fabricating multi-component nanowires in accordance with the present invention includes the steps of: (a) preparing an anodized aluminum oxide nanotemplate having a plurality of pores; (b) forming an electrode layer on one surface of the anodized aluminum oxide nanotemplate; (c) injecting the anodized aluminum oxide nanotemplate in a predetermined multi-component solution and then growing multi-component nanowires through the pores of the anodized aluminum oxide nanotemplate by an electroplating process in which the anodized aluminum oxide nanotemplate is used as a cathode; and (d) removing the anodized aluminum oxide nanotemplate. | 07-01-2010 |
Ji Hyun Moon, Jeonju-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090101106 | METHOD OF CONTROLLING HEATING DURING IDLING OF VEHICLE - A method of controlling heating while a vehicle is idling is disclosed. The method comprises: determining whether a state of readiness for idle heating exists; determining whether the vehicle is slopped; determining whether a temperature outside the vehicle reaches a winter temperature; and thereby operating an idle heating mode when all above criteria are met. | 04-23-2009 |
Ji Hyun Park, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090023460 | System and method for setting up P2P communication group in cellular system, and P2P communication system and method using P2P communication group - Disclosed herein are a system and method for setting up a Peer-to-Peer (P2P) communication group in a cellular system, and a P2P communication system and method using the P2P communication group. The system for setting up a P2P communication group for a terminal in a cellular system including a base station and the terminals includes a location detection unit, a location information transmission unit, a control information reception unit, and a final group setup unit. The location detection unit detects the location of a terminal. The location information transmission unit sends information about the location, detected by the location detection unit, to the base station. The control information reception unit receives information about a preliminary P2P communication group set up by the base station based on the location information. The final group setup unit sets up a final P2P communication group based on the preliminary P2P communication group. | 01-22-2009 |
| 20110189087 | TMPRSS4-Specific Human Antibody - The present invention relates to a transmembrane protease, serine (TMPRSS4)-specific human antibody, and more particularly to a human antibody including a complementarity determining region (CDR) and a framework region (FR) derived from a human antibody specifically bound to TMPRSS4. The TMPRSS4-specific human antibody expressed in the various kinds of cancer cells of the present invention may be used in diagnosis of the cancer, classification of the disease, visualization, treatment, and prognostic evaluation. | 08-04-2011 |
Ji Hyun Ryu, Incheon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090297264 | ROAD MARKER - A road marker according to exemplary embodiments of the present invention has advantages that exterior impact transmitted from a tire may be absorbed by elastic force of a spring as a consequence of a transparent cover being completely inserted in an upper housing when a vehicle passes on a road marker. The road marker has further advantages in that a vehicle load may not be transmitted to a guide cover and thus breakage of the road marker may be prevented. | 12-03-2009 |
Ji Hyun Seo, Kyeongki-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090029523 | Method of Fabricating Flash Memory Device - The invention relates to a method of fabricating flash memory device. In accordance with an aspect of the invention, the method includes forming a gate insulating layer, a first conductive layer, and an isolation mask over a semiconductor substrate. The isolation mask is patterned to expose regions in which an isolation layer will be formed. The first conductive layer, the gate insulating layer, and the semiconductor substrate are etched using the patterned isolation mask to form trenches. A liner oxide layer is formed on the resulting structure including the trenches. The trenches in which the liner oxide layer is formed are filled with an insulating layer. A planarizing process and a cleaning process are carried out such that wing spacers covering the gate insulating layer are formed at top edge portions of the isolation layer, thereby forming the isolation layer. | 01-29-2009 |
Ji Hyun Seo, Bucheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100075477 | Method of Manufacturing Semiconductor Device - An embodiment of the disclosure relates to a method of manufacturing semiconductor devices. According to this embodiment, a tunnel insulating layer, a conductive layer for a floating gate, and a hard mask layer are sequentially formed over a semiconductor substrate. Isolation trenches are formed by etching the hard mask layer, the conductive layer for the floating gate, the tunnel insulating layer, and the semiconductor substrate. Isolation structures are formed by filling the isolation trenches with an insulating layer. Upper sidewalls of the isolation trenches are exposed by etching predetermined thickness of the isolation structures. Ion implantation regions are formed in the exposed upper sidewalls of the isolation trenches by performing an ion implantation process. | 03-25-2010 |
Ji Hyun Seo, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100054044 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device includes setting an initial cell current level, performing program and erase operations for each word line of a memory block, storing the cycling number of the program and erase operations, comparing the cycling number with a critical cycling number of the program and erase operations, lowering the initial cell current level when the cycling number are larger than the critical cycling number, and changing a program operation option based on the lowered initial cell current level | 03-04-2010 |
| 20100124121 | METHOD OF ERASING FLASH MEMORY DEVICE - In a method of erasing a flash memory device according to an aspect of this disclosure, an erase operation is performed to lower threshold voltages of memory cells to a voltage level less than a first voltage. A first soft program operation is performed until a threshold voltage of any one of the memory cells reaches a second voltage higher than the first voltage. A second soft program operation is performed until a threshold voltage of any one of the memory cells reaches a third voltage higher than the second voltage. | 05-20-2010 |
Ji-Hyun Ahn, Jeonju-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080215939 | Semiconductor memory device with fail-bit storage unit and method for parallel bit testing - There are provided a semiconductor memory device and a method for testing the same, in which when a plurality of semiconductor memory devices are under test, tester equipment can detect which one of the semiconductor memory devices fails without a separate fail memory. The semiconductor memory device with a memory cell array includes a comparing circuit configured to compare data read after having been written for parallel bit testing with each other and outputting comparison result data; and a storage and output unit configured to latch, as pass/fail data, the comparison result data output from the comparing circuit, simultaneously output the latched comparison result data via a plurality of outputs when an enable signal is activated, and simultaneously output independently applied parallel bit test comparison data via the plurality of outputs when the enable signal is not activated. | 09-04-2008 |
Ji-Hyun Jeong, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100108971 | Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby - Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer. | 05-06-2010 |
| 20100159675 | METHOD FABRICATING NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes; forming a first sacrificial layer pattern including a first open area that extends in a first direction on a lower dielectric layer, forming a pre-lower dielectric layer pattern including a recess that extends in the first direction using the first sacrificial layer pattern, forming a second sacrificial layer pattern including a second open area that extends in a second direction on the pre-lower dielectric layer pattern and the first sacrificial layer pattern, wherein the second open area intersects the first open area, forming a lower dielectric layer pattern including contact holes spaced apart in the recess using the first sacrificial layer pattern and second sacrificial layer pattern, wherein the contact holes extend to a bottom of the lower dielectric layer pattern, and forming a bottom electrode in the contact hole. | 06-24-2010 |
| 20100181549 | Phase-Changeable Random Access Memory Devices Including Barrier Layers and Metal Silicide Layers - A PRAM device may include an insulating interlayer, a diode, a metal silicide layer, a barrier spacer, an outer spacer, a lower electrode, a phase-changeable layer and an upper electrode. The insulating interlayer may be formed on a substrate. The insulating interlayer may have a contact hole. The diode may be formed in the contact hole. The metal silicide layer may be formed on the diode. The barrier spacer may be formed on an upper surface of the metal silicide layer and a side surface of the contact hole. The outer spacer may be formed on the barrier spacer. The lower electrode may be formed on the barrier spacer. The phase-changeable layer may be formed on the lower electrode. The upper electrode may be formed on the phase-changeable layer. | 07-22-2010 |
| 20100227449 | METHOD OF FORMING MEMORY DEVICE - A variable resistance memory device, and a method of forming the same. The method may include forming a lower electrode on a substrate, stacking a first etch stop layer and a second etch stop layer on the substrate, forming an insulating layer on the second etch stop layer, forming a recessing region to expose the lower electrode by patterning the insulating layer and the first and second etch stop layer, forming a variable resistance material layer in the recess region, and forming an upper electrode on the variable resistance material layer. The first etch stop layer can have an etching selectivity with respect to the second etch stop layer. | 09-09-2010 |
| 20110248235 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate and a first insulating layer on the substrate. The first insulating layer includes a first opening therein. A lower electrode is provided in the first opening and protrudes from a surface of the first insulating layer outside the first opening. An electrode passivation pattern is provided on a sidewall of the lower electrode that protrudes from the surface of the first insulating layer. A second insulating layer is provided on the first insulating layer and includes a second opening therein at least partially exposing the lower electrode. A variable resistance material layer extends into the second opening to contact the lower electrode. The electrode passivation layer electrically separates the sidewall of the lower electrode from the variable resistance material layer. The electrode passivation pattern is formed of a material having an etching selectivity to that of the second insulating layer. Related fabrication methods are also discussed. | 10-13-2011 |
| 20120092946 | MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING DISCHARGE LINES AND METHODS OF FORMING - A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line. | 04-19-2012 |
Ji-Hyun Jung, Gyeongbuk KR
| Patent application number | Description | Published |
|---|---|---|
| 20110063537 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME - The liquid crystal display device includes a first substrate and a second substrate, a gate line and a data line on the first substrate to define a pixel region, a pixel transistor formed at the intersection of the gate line and the data line, a pixel electrode formed in the pixel region, a first storage capacitor connected to the pixel electrode, a switching line formed on the first substrate, a read out line formed on the first substrate, a second storage capacitor formed on the first substrate, a switching transistor including a gate electrode connected to the second storage capacitor, a drain electrode connected to the read out line, and a source electrode connected to a driving voltage line, a first column spacer formed on the second substrate, and a common electrode formed on the first column spacer thereby forming a sensing capacitor. | 03-17-2011 |
Ji-Hyun Jung, Gwangju-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090057001 | INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF - An IC package includes: a multi-layered PCB having a plurality of insulating layers and a plurality of conductive pattern layers stacked in sequence and a plurality of via-holes formed through the plurality of the insulating layers for an electrical connection between the layers; and an IC chip disposed in a core insulating layer of the plurality of the insulating layers to be embedded in the multi-layered PCB and including a plurality of input/output pads on their surface. The input/output pads disposed at an outermost area of the IC chip are coupled to outer terminals by connection members without passing through said via-hole, the remaining input/output pads except for the input/output pads disposed at the outermost area of the IC chip are coupled to the outer terminals through the via-hole. | 03-05-2009 |
| 20100007475 | VIDEO REPRODUCTION APPARATUS AND METHOD FOR PROVIDING HAPTIC EFFECTS - An apparatus and method for allowing a user to dynamically enjoy a video. A difference between image data is computed at every preset unit of time and a vibration corresponding to the computed difference is generated so that the user can sense a motion change of an object within the video. Upon video reproduction, scenes are displayed by applying the lighting effect of a strobe light or the like between the scenes to be reproduced. Upon video reproduction, more enjoyment and various haptic effects can be provided to the user. | 01-14-2010 |
Ji-Hyun Kang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100151079 | TRANS FATTY ACID FREE FAT FOR MARGARINE PRODUCED BY ENZYMATIC INTERESTERIFICATION AND METHOD FOR PREPARING THE SAME - The present invention can provide margarine oil with the enzymatic interesterification reaction, in which trans fatty acid, different from the existing partially hydrogenerated oil, is not formed in the process, and it has solid fat value profile and melting point corresponding to that of partially hydrogenerated oil and contains less than 1% of trans fatty acid, less than 27% of palmitic acid, more than 99% of triglyceride, less than 1% of diglyceride and monoglyceride, less than 1% of trans fatty acid and based on total fatty acid content. Accordingly, the margarine oil of the present invention is eco-friend and has lower trans fatty acid compared to the existing partially hydrogenerated oil and is easily to use for substituting in the ratio of 1:1 because of its physical properties corresponding to that of partially hydrogenerated oil for margarine oil and is also nutritionally excellent since it has lower palmitic acid content than natural palm oil which is usually used as a substitute for the existing margarine oil such as partially hydrogenerated oil. | 06-17-2010 |
| 20100178386 | TRANS FATTY ACID FREE FAT FOR FRYING PRODUCED BY ENZYMATIC INTERESTERIFICATION AND METHOD FOR PREPARING THE SAME - The present invention can provide frying oil with the enzymatic interesterification reaction, in which trans fatty acid is not formed in the process different from the existing partially hydrogenerated oil and the frying oil contains less than 1% of trans fatty acid content and less than 27% of palmitic acid based on total fatty acid content and has solid fat content at temperature of 37.8° C. and melting point corresponding to that of partially hydrogenerated oil. Accordingly, the frying oil of the present invention is eco-friend and has lower trans fatty acid compared to the existing partially hydrogenerated oil and has higher triglyceride content without side reaction, and is also nutritionally excellent since it has lower palmitic acid content than natural palm oil which is usually used as a substitute for the existing frying oil such as partially hydrogenerated oil, and has taste corresponding to partially hydrogenerated oil. | 07-15-2010 |
| 20110262592 | COCOA BUTTER EQUIVALENTS PRODUCED BY THE ENZYMATIC INTERESTERIFICATION PROCESS AND METHOD FOR PREPARING THE SAME - The present invention relates to a process for preparing hard butter having high SOS content by mixing oil for preparing butter with fatty acid or fatty acid ester, adding 1,3 regio-specific enzymes to the obtained mixture to carry out interesterification, distilling the obtained reactants to remove fatty acid, ethyl ester, and monoglyceride and diglyceride formed after the reaction and fractionally extracting the obtained reactants to separate a solid phase, and to cocoa butter equivalents prepared by the hard butter and a process for preparing the same in which the cocoa butter equivalents can replace existing import cocoa butter equivalents with 1:1 because of its equivalent chemical properties, and have no difference in taste and properties with natural cocoa butter and also have lower trans fatty acid. Hard butter according to the present invention can make desired triglyceride structure in oil based on the reaction conditions and have a improved purity and yield in the whole process by recycling all of byproduct other than major product in the distillation and fractional distillation process and is eco-friendly matter by using the enzymatic interesterification reaction, and also cocoa butter equivalents made by the hard butter is characterized in replacing existing import cocoa butter equivalents with 1:1 because of its equivalent chemical composition and properties in the production of chocolate with no difference in taste. | 10-27-2011 |
Ji-Hyun Kang, Kyunggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100120102 | ENANTIOSELECTIVE EPOXIDE HYDLROLASE AND METHOD FOR PREPARING AND ENANTIOPURE EPOXIDE USING THE SAME - The present invention relates to enantioselective epoxide hydrolase proteins isolated from marine microorganisms, which has high enantioselectivity to various epoxide substrates, and a method of preparing the epoxides with high enantio-purity by using the epoxide hydrolases. The enantioselective hydrolase protein of the present invention can be applied for the preparation of enantiopure epoxides with high bioactivity at a high yield. | 05-13-2010 |
Ji-Hyun Kang, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100272689 | Protease Having Algicidal Activity, Gene Encoding the Same and Algicidal Formulation Comprising the Same - The present invention relates to a protease having algicidal activity, a gene encoding the same and algicidal formulation comprising the same. The protease according to the present invention showed high algicidal activity. Therefore, the protease can be used treatment of red tide in marine region of red tide occurrence. | 10-28-2010 |
Ji-Hyun Kim, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110227616 | PHASE LOCKED LOOP CIRCUIT, METHOD OF DETECTING LOCK, AND SYSTEM HAVING THE CIRCUIT - Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal. | 09-22-2011 |
| 20110227617 | PHASE LOCKED LOOP CIRCUIT AND SYSTEM HAVING THE SAME - A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other. | 09-22-2011 |
Ji-Hyun Kim, Incheon KR
| Patent application number | Description | Published |
|---|---|---|
| 20090138198 | APPARATUS AND METHOD FOR SHARING THE LANDMARK INFORMATION OF THE LOCATION SERVICE USING A JAVA RECORD MANAGEMENT SYSTEM IN A WIRELESS COMMUNICATION TERMINAL - A method and an apparatus for sharing landmark information of a location service in a wireless communication terminal are provided. The method includes obtaining location information in a JAVA application and storing the landmark information based the location information using a backup database format in a file system region. | 05-28-2009 |
Ji-Hyun Kim, Bupyeong-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20090143011 | METHOD AND APPARATUS FOR IDENTIFYING JAVA PUSH REQUEST EQUIPMENTS USING BLUETOOTH IN A MOBILE COMMUNICATION TERMINAL - Provided are an identifying method and an apparatus for identifying a plurality of JAVA™ PUSH request terminals using Bluetooth® communication in a mobile communication terminal. According to the method, acquiring information records for performing JAVA™ PUSH about a plurality of terminals by requesting a service search through a Logical Link Control and Adaption Protocol (L2CAP) connection between the mobile communication terminal and the plurality of JAVA™ PUSH request terminals and displaying unique identification information of the plurality of JAVA™ PUSH request terminals by checking the information records of the plurality of JAVA™ PUSH request terminals. | 06-04-2009 |
Ji-Hyun Kwon, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100201668 | Gate Drive Circuit and Display Apparatus Having the Same - Gate drive circuit includes a plurality of stages connected one after another to each other. An m-th stage includes a pull-up section outputting a first clock signal as a gate signal of the m-th stage to an output terminal, a pull-down section applying a low voltage to the output terminal, a carry section outputting the first clock signal as a carry signal of the m-th stage in response to the high voltage of the first node signal, a first carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to the high voltage of the first clock signal and a second carry holding section maintaining the carry signal of the m-th stage at the low voltage in response to a high voltage of the second clock signal. | 08-12-2010 |
| 20100208157 | LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF - A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a plurality of pixels arranged in a matrix shape. Each of the pixels include a first subpixel and a second subpixel. The pixels include a first thin film transistor transmitting a first data voltage to the first subpixel. The first thin film transistor includes a first source electrode, a first drain electrode, and a first gate electrode. The pixels include a second thin film transistor transmitting a second data voltage to the second subpixel. The second thin film transistor includes a second source electrode, a second drain electrode, and a second gate electrode. A relative position of the first drain electrode with respect to the first source electrode is opposite to a relative position of the second drain electrode with respect to the second source electrode in each pixel. | 08-19-2010 |
Ji-Hyun Park, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110042797 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package. | 02-24-2011 |
| 20110149493 | STACKED SEMICONDUCTOR PACKAGES, METHODS OF FABRICATING THE SAME, AND/OR SYSTEMS EMPLOYING THE SAME - An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. | 06-23-2011 |
Ji-Hyun Park, Suseong-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20100166878 | COMPOSITION COMPRISING BEE VENOM FOR THE TREATMENT OF ATHEROSCLEROSIS - The present invention provides bee venom which can decrease expression levels of sclerotic factors, inflammatory factors and vascular adhesion factors associated with atherosclerosis, and a pharmaceutical composition comprising the bee venom as an active ingredient for the treatment of the atherosclerosis. When the bee venom was administered to laboratory animal models of atherosclerosis, the total cholesterol and neutral lipid were decreased, high-density cholesterol was maintained or even increased, the expression levels of TNF-α and IL-β as inflammation-associated cytokines were decreased in the blood, the expression levels of fibrosis-associated cytokines and vascular adhesion factors were decreased in the main artery and the heart, the plaque deposition generally caused by the atherosclerosis was decreased, and the expression levels of intercellular adhesion molecules (ICAM) and vascular cell adhesion molecules (VCAM), TGF-β1 and fibronectin as fibrosis-related cytokines were decreased. | 07-01-2010 |
Ji-Hyun Yoo, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080261282 | Fermentation Process for Preparing Coenzyme Q10 by the Recombinant Agrobacterium tumefaciens - The present invention relates to a transformed | 10-23-2008 |