Patent application number | Description | Published |
20120159044 | NON-VOLATILE MEMORY SYSTEM WITH BLOCK PROTECTION FUNCTION AND BLOCK STATUS CONTROL METHOD - A non-volatile memory system with a block protection function includes a memory area including a first memory area including a plurality of blocks and a second memory area, and a controller configured to record data, which corresponds to status information on the plurality of blocks, in the second memory area, and read the data from the second memory area. | 06-21-2012 |
20120182812 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device that may perform a second operation during a first operation comprises a command decoder for generating a decoded command signal, a suspend pulse and a resume pulse, and a storage unit for storing the decoded address signal, the decoded command signal and a data signal in response to the suspend pulse and providing the decoded address signal, the decoded command signal and the decoded data signal as a stored address signal, a stored command signal and a stored data signal, respectively, in response to the resume pulse. | 07-19-2012 |
20120287728 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode. | 11-15-2012 |
20130322191 | SEMICONDUCTOR DEVICE CAPABLE OF BLOCK PROTECTION - A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal. | 12-05-2013 |
20140164682 | NONVOLATILE MEMORY APPARATUS, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME - Provided is a nonvolatile memory apparatus which writes data into a memory cell according to a program and verify (PNV) operation, wherein the nonvolatile memory apparatus performs the PNV operation for first data during a first time, and performs a plurality of PNV operations for second data during the first time. | 06-12-2014 |
20140241043 | ELECTRONIC DEVICE AND METHOD FOR OPERATING ELECTRONIC DEVICE - An electronic device comprising a semiconductor memory unit that may include a plurality of data transfer lines; a plurality of columns including a plurality of memory cells; at least one redundancy column including a plurality of redundancy memory cells and configured to replace at least one column among the plurality of columns; a repair select information generation unit configured to store a column address of the at least one column to be replaced among the plurality of columns and generate a plurality of repair select information in response to the stored column address; and a plurality of repair selection units connected with data transfer lines corresponding to them among the plurality of data transfer lines, columns corresponding to them among the plurality of columns and the at least one redundancy column, and each configured to electrically connect a column selected among a column corresponding to it and the at least one redundancy column, to a data transfer line corresponding to it, in response to repair select information corresponding to it among the plurality of repair select information. | 08-28-2014 |
20140286115 | NONVOLATILE RANDOM ACCESS MEMORY - According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command. | 09-25-2014 |
20150063017 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode. | 03-05-2015 |