Patent application number | Description | Published |
20120083077 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer. | 04-05-2012 |
20120153291 | Vertical Memory Devices Including Indium And/Or Gallium Channel Doping - A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed. | 06-21-2012 |
20120156848 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY DEVICE AND CONTACT PLUGS OF SEMICONDUCTOR DEVICE - A method of manufacturing a non-volatile memory device includes alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate, forming first openings exposing the substrate, forming sidewall insulating layers on sidewalls of the first openings, and forming channel regions on the sidewall insulating layers. The first openings penetrate the interlayer sacrificial layers and the interlayer insulating layers. The sidewall insulating layers have different thicknesses according to distances from the substrate. | 06-21-2012 |
20120166450 | SEARCH SYSTEM AND SEARCH METHOD FOR RECOMMENDING REDUCED QUERY - A search system includes a non-transitory computer-readable storage device, and a computing device. A term extracting unit causes the computing device to extract multiple terms from an input query, a weight computing unit causes the computing device to compute a weight for each of the multiple terms, and a reduction query recommending unit causes the computing device to remove at least one term from the multiple terms, based on the weight, and to provide at least one reduced query using remaining terms. A search method that uses a computing device to provide a reduced query, the method includes extracting multiple terms from an input query; computing, by the computing device, a weight of each of the multiple terms; and removing at least one term from the multiple terms, based on the weight, and providing at least one reduced query generated using remaining terms out of the multiple terms. | 06-28-2012 |
20120267702 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A device includes a first GSL, a plurality of first word lines, a first SSL, a plurality of first insulation layer patterns, and a first channel. The first GSL, the first word lines, and the first SSL are spaced apart from each other on a substrate in a first direction perpendicular to a top surface of a substrate. The first insulation layer patterns are between the first GSL, the first word lines and the first SSL. The first channel on the top surface of the substrate extends in the first direction through the first GSL, the first word lines, the first SSL, and the first insulation layer patterns, and has a thickness thinner at a portion thereof adjacent to the first SSL than at portions thereof adjacent to the first insulation layer patterns. | 10-25-2012 |
20130273704 | METHODS OF FORMING A POLYSILICON LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer. | 10-17-2013 |
20140084357 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer. | 03-27-2014 |
20150194440 | Nonvolatile Memory Devices And Methods Of Fabricating The Same - A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer. | 07-09-2015 |