Patent application number | Description | Published |
20080212391 | LOW POWER MULTI-CHIP SEMICONDUCTOR MEMORY DEVICE AND CHIP ENABLE METHOD THEREOF - A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are provided. The individual semiconductor chips of the device are activated and deactivated in accordance with internal chip enable signals. | 09-04-2008 |
20090059666 | MEMORY CELL ARRAY AND NON-VOLATILE MEMORY DEVICE - A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell arrays, and each of the sub-memory banks includes multiple physical sectors. The sense amplifiers are dedicated to the sub-memory banks, respectively. | 03-05-2009 |
20090059667 | MEMORY CELL ARRAY AND NON-VOLATILE MEMORY DEVICE - A memory cell array is disclosed which includes a plurality of memory banks, each memory bank including a plurality of logical sectors. The memory cell array includes a plurality of sub-memory banks, wherein each one of the plurality of sub-memory banks includes a plurality of physical sectors, and each one of the plurality of physical sectors is part of one of the plurality of logical sectors, and a plurality of sense amplifiers respectively associated with the plurality of sub-memory banks. | 03-05-2009 |
20090289712 | AMPLIFIER CIRCUIT - An amplifier circuit includes first and second transistor circuits, a current supply unit, and a current sink unit. The first transistor circuit is operatively responsive to a first input signal, and the second transistor circuit is operatively responsive to a second input signal. The current supply unit includes at least two symmetrically configured current mirrors connected to a source voltage, and provides a first current to the first transistor circuit and a second current to the second transistor circuit, where a magnitude of the first and second currents is the same. The current sink unit is responsive to an enable signal to sink the first and second currents supplied to the first and second transistor circuits to a ground voltage. | 11-26-2009 |
20090296483 | NONVOLATILE MEMORY DEVICE WITH EXPANDED TRIMMING OPERATIONS - A nonvolatile memory device includes a trimming cell array storing trimming data for a plurality of operating modes, a trimming cell sense amplifier sensing the trimming data and a trimming cell latch storing the sensed trimming data. A plurality of trimming circuits performs trimming operations in response to a trimming control signals derived from trimming data. A single temporary trimming control logic unit receives externally provided control data and controls operation of a single summation circuit. The summation circuit controls the operation of the trimming circuits by respectively and selectively varying the trimming control signal provided to each one of the plurality of trimming circuits in response to the externally provided control data. | 12-03-2009 |
20100238739 | NOR FLASH MEMORY DEVICE AND RELATED METHODS OF OPERATION - A NOR flash memory device is programmed by selecting one of a plurality of global bit lines and sequentially selecting a plurality of local bit lines commonly connected with the selected global bit line to supply a program voltage to memory cells. | 09-23-2010 |
20100277978 | FLASH MEMORY DEVICE HAVING IMPROVED READ OPERATION SPEED - Provided is a flash memory device. The flash memory device includes: a memory cell storing multi-bit data; a reference bias voltage supply circuit generating a reference bias voltage; an sense amplifier sensing the multi-bit data stored in the memory cell using the reference bias voltage; and a control circuit controlling the reference bias voltage supply circuit. The control circuit controls the reference bias voltage supply circuit to allow the reference bias voltage to be developed according to a change of a main word line voltage applied to the memory cell during a read operation. | 11-04-2010 |
20100278001 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory core; a charge pump circuit providing a high voltage to the memory core; and a charge pump control circuit operating the charge pump circuit by a standby mode and measuring an operation time value of the standby mode. The charge pump control circuit controls the standby mode of the charge pump circuit using the time value. | 11-04-2010 |