| Patent application number | Description | Published |
|---|
| 20080279016 | SIMPLIFIED-DOWN MODE CONTROL CIRCUIT UTILIZING ACTIVE MODE OPERATION CONTROL SIGNALS - A power-down control circuit utilizes the control signals employed in an active mode operation to operate when a power-down mode entry command is received during an active mode operation. The circuit is simplified requiring less area for devising the control circuit while lowering power consumption. The power-down control circuit in a semiconductor memory device includes at least a clock enable buffer unit, an external clock buffer unit, a latch unit, a control circuit for controlling internally operating clocks employed in active mode operation by using a control signal used in the active mode operation when a power-down mode entry command is received during the active mode operation, and a clock enable generation circuit for outputting clock enable signals for enabling entry to the power-down mode by using the clock control signals, when the external clock pulse signal is low level. | 11-13-2008 |
| 20080304336 | SEMICONDUCTOR MEMORY DEVICE WITH ZQ CALIBRATION - A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal generating unit for generating a test mode signal which is enabled in the test mode for outputting the calibration codes, and a test mode control unit for selectively outputting the data or the calibration codes in response to the test mode signal. | 12-11-2008 |
| 20090002003 | PROBE-TESTING DEVICE AND METHOD OF SEMICONDUCTOR DEVICE - A probe-testing device includes probe tips configured to apply inputs to pads of a semiconductor chip, wherein one of the probe tips is connected to a calibration pad for impedance adjustment and a calibration resistor is connected thereto. | 01-01-2009 |
| 20090003096 | Semiconductor memory device - A semiconductor memory device is provided to improve the tAA characteristics. The semiconductor memory device includes: a discrimination signal generating unit for generating a first discrimination signal denoting a write operation of the semiconductor memory device; a selective delay unit for delaying a command-group signal in response to a second discrimination signal; and a fuse unit for generating the second discrimination signal based on the first discrimination signal, the second discrimination signal determining whether the selective delay unit selectively delays the command-group signal in response to the first discrimination signal. | 01-01-2009 |
| 20090013225 | TEST MODE CONTROL CIRCUIT - Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated. | 01-08-2009 |
| 20090016119 | Memory device performing write leveling operation - A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit. | 01-15-2009 |
| 20090115449 | ON DIE TERMINATION DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes. | 05-07-2009 |
| 20090115480 | Clock control circuit and data alignment circuit including the same - A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal. | 05-07-2009 |
| 20090116313 | DATA OUTPUT CONTROL CIRCUIT - A data output control circuit includes a data output control circuit configured to compensate a delay amount of a system clock on a clock path when a delay locked loop (DLL) circuit is enabled in such a state that the semiconductor memory device exits a reset state in response to an active signal, and to determine an output timing of data corresponding to a read command by counting the system clock and a DLL clock outputted from the DLL circuit | 05-07-2009 |
| 20090116316 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a plurality of test-off units configured to control the test operations of the internal circuits to be disabled in response to a test-off signal. | 05-07-2009 |
| 20090172479 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals. | 07-02-2009 |
| 20090267683 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE - Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal. | 10-29-2009 |
