| Patent application number | Description | Published |
|---|
| 20100193877 | Memory Array Structure With Strapping Cells - A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells. | 08-05-2010 |
| 20100213552 | Cell Structure for Dual Port SRAM - An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected. | 08-26-2010 |
| 20110069527 | ROM CELL AND ARRAY STRUCTURE - A semiconductor memory cell array includes an elongated continuous active region. First and second pass transistors are formed in the elongated continuous active region and form part of first and second adjacent memory cells, respectively, of a column of memory cells in the array. An isolation transistor is formed in the elongated continuous active region between the first and second pass transistors and biased in an off state. First and second word lines are coupled to the gates of the pass transistors for applying a reading voltage. The array includes a differential bit line pair including first and second bit lines, a first logic value being encoded into the memory cells by connecting the pass transistors to the first bit line and a second logic value being encoded into the memory cells by connecting the pass transistors to the second bit line. | 03-24-2011 |
| 20110075470 | EMBEDDED SRAM STRUCTURE AND CHIP - An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one. | 03-31-2011 |
| 20110133285 | SRAM Structure with FinFETs Having Multiple Fins - A static random access memory (SRAM) cell includes a straight fin and a bended fin physically disconnected from the straight fin. The bended fin has a first portion and a second portion parallel to the straight fin. The distance between the first portion of the bended fin and the straight fin is smaller than the distance between the second portion of the bended fin and the straight fin. The SRAM cell includes a pull-down transistor including a portion of a first gate strip, which forms a first and a second sub pull-down transistor with the straight fin and the first portion of the bended fin, respectively. The SRAM cell further includes a pass-gate transistor including a portion of a second gate strip, which forms a first sub pass-gate transistor with the straight fin. The pull-down transistor includes more fins than the pass-gate transistor. | 06-09-2011 |
| 20110182098 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE SAME - An integrated circuit including a first memory array and a logic circuit coupled with the first memory array. All active transistors of all memory cells of the first memory array and all active transistors of the logic circuit are Fin field effect transistors (FinFETs) and have gate electrodes arranged along a direction a first longitudinal direction. | 07-28-2011 |
| 20110195564 | Memory Cell Layout - A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved. | 08-11-2011 |
| 20110222332 | Fully Balanced Dual-Port Memory Cell - The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU | 09-15-2011 |
