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Jesse E. Craig
Jesse E. Craig, Cambridge, MA US
| Patent application number | Description | Published |
|---|---|---|
| 20110016326 | Chip Lockout Protection Scheme for Integrated Circuit Devices and Insertion Thereof - A system for implementing a chip lockout protection scheme for an IC device includes an on-chip password register that stores a password externally input by a user; an on-chip security block that generates a chip unlock signal, depending on whether the externally input password matches a correct password; an on-chip false data generator; an input protection scheme configured to gate the external data inputs to functional chip circuitry upon entry of the correct password; and an output protection scheme in communication configured to steer true chip data to external outputs of the IC device upon entry of the correct password, and to steer false data generated by the false data generator to the external outputs upon entry of an incorrect password. The false generated by the false data generator is deterministic and based upon external data inputs, thereby obfuscating whether or not the correct password has been entered. | 01-20-2011 |
Jesse E. Craig, South Burlington, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090210837 | VERIFYING NON-DETERMINISTIC BEHAVIOR OF A DESIGN UNDER TEST - The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks. | 08-20-2009 |
| 20090251474 | VIRTUAL COMPUTING AND DISPLAY SYSTEM AND METHOD - A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of graphic commands. The system further includes at least one communication network which directly receives the graphics processing unit command stream from each of the microprocessor-based devices and transfers each of the generated graphics processing unit command streams via a respective active channel, at least one multi-core adaptive display server which receives and processes the graphics processing unit command streams, and at least one display which receives the packets via the at least one active channel per user session and displays at least one image. The at least one active channel connects a respective microprocessor-based device, the communication network, the at least one multi-core adaptive display server and the at least one display. | 10-08-2009 |
Jesse E. Craig, S. Burlington, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20080225431 | Multi-Arm Disk Drive System Having Interleaved Read/Write Operations and Method of Controlling Same - A hard disk drive system that includes one or more rotating data storage platters, a drive controller and multiple actuator assemblies and corresponding respective read/write heads. The actuator assemblies are separately moveable for performing separate data seeks. The controller is configured to interleave the seek and read/write operations of the multiple actuator assemblies and read/write heads with one another. | 09-18-2008 |
| 20090172627 | Design Structure for a Clock System for a Plurality of Functional Blocks - A design structure for a clock system for a plurality of functional blocks designed using a method of reducing peak power that utilizes connectivity and/or timing information among a plurality of design partitions of an integrated circuit system to create a clock system that reduces peak power consumption across the system. The method used to create the design structure includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals. | 07-02-2009 |
Jesse E. Craig, Burlington, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20080270965 | METHOD OF REDUCING PEAK POWER CONSUMPTION IN AN INTEGRATED CIRCUIT SYSTEM - A method that utilizes connectivity and/or timing information among a plurality of design partitions of an circuit system to create a clock system that reduces peak power consumption across the system. The method includes sorting the design partitions according to a connectivity model, a timing model, or both, and assigning interleaved clock signals as a function of the design partition ordering. The clock system is created as a function of the interleaved clock signals. | 10-30-2008 |
| 20090031111 | METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS - A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions. | 01-29-2009 |
| 20090125704 | DESIGN STRUCTURE FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS - A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions. | 05-14-2009 |