| Patent application number | Description | Published |
|---|
| 20110072211 | Hardware For Parallel Command List Generation - A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit. | 03-24-2011 |
| 20110072245 | HARDWARE FOR PARALLEL COMMAND LIST GENERATION - A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit. | 03-24-2011 |
| 20110080407 | PIXEL SHADER OUTPUT MAP - One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render targets. A shader program header (SPH) file provides per-component mask bits for each render target. Each enabled mask bit indicates that the pixel shader generates the corresponding component as an output to the raster operations unit. In the hardware, the per-component mask bits are combined with the applications programming interface (API)-level per-component write masks to determine the components that are updated by the shader program. The combined mask is used as the write enable bits for components in one or more render targets. One advantage of the combined mask is that the components that are not updated are not forwarded from the pixel shader to the ROP, thereby saving bandwidth between those processing units. | 04-07-2011 |
| 20110084976 | Shader Program Headers - One embodiment of the present invention sets forth a technique for configuring a graphics processing pipeline (GPP) to process data according to one or more shader programs. The method includes receiving a plurality of pointers, where each pointer references a different shader program header (SPH) included in a plurality of SPHs, and each SPH is associated with a different shader program that executes within the GPP. For each SPH included in the plurality of SPHs, one or more GPP configuration parameters included in the SPH are identified, and the GPP is adjusted based on the one or more GPP configuration parameters. | 04-14-2011 |
| 20110084977 | STATE SHADOWING TO SUPPORT A MULTI-THREADED DRIVER ENVIRONMENT - One embodiment of the present invention sets forth a technique for tracking and filtering state change methods provided to a graphics pipeline. State shadow circuitry at the start of the graphics pipeline may be configured in different modes. A track mode is used to capture the current state by storing state change methods that are transmitted to the graphics pipeline. A passthrough mode is used to provide different state data to the graphics pipeline without updating the current state stored in the state shadow circuitry. A replay mode is used to restore the current state to the graphics pipeline using the state shadow circuitry. Additionally, the state shadow circuitry may also be configured to filter the state change methods that are transmitted to graphics pipeline by removing redundant state change methods. | 04-14-2011 |
| 20110087864 | PROVIDING PIPELINE STATE THROUGH CONSTANT BUFFERS - One embodiment of the present invention sets forth a technique for providing state information to one or more shader engines within a processing pipeline. State information received from an application accessing the processing pipeline is stored in constant buffer memory accessible to each of the shader engines. The shader engines can then retrieve the state information during execution. | 04-14-2011 |
| 20110242119 | GPU Work Creation and Stateless Graphics in OPENGL - One embodiment of the present invention sets forth a method for generating work to be processed by a graphics pipeline residing within a graphics processor. The method includes the steps of receiving an indication that a first graphics workload is to be submitted to a command queue associated with the graphics processor, allocating a first portion of shader accessible memory for one or more units of state information that are necessary for processing the first graphics workload, populating the first portion of shader accessible memory with the one or more units of state information, and transmitting to the command queue of the graphics processor the one or more units of state information stored within the first portion of shader accessible memory, wherein the first graphics workload is processed within the graphics pipeline based on the one or more units of state information. | 10-06-2011 |
| 20110242125 | BINDLESS MEMORY ACCESS IN DIRECT 3D - One embodiment of the present invention sets for a method for accessing data objects stored in a memory that is accessible by a graphics processing unit (GPU). The method comprises the steps of creating a data object in the memory based on a command received from an application program, transmitting a first handle associated with the data object to the application program such that data associated with different graphics commands can be accessed by the GPU, wherein the first handle includes a memory address that provides access to only a particular portion of the data object, receiving a first graphics command as well as the first handle from the application program, wherein the first graphics command includes a draw command or a compute grid launch, and transmitting the first graphics command and the first handle to the GPU for processing. | 10-06-2011 |
