| Patent application number | Description | Published |
|---|
| 20080265342 | TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a T-shaped gate on the gate oxide layer. A first charge storage layer is disposed at one side of and under the T-shaped gate. A second charge storage layer, which is separated from the first charge storage layer by a bottom portion of the T-shaped gate and the gate oxide layer, is disposed at the other side of and under the T-shaped gate. An insulating layer is disposed between the T-shaped gate and the gate oxide layer. A first source/drain region is disposed at one side of the T-shaped gate within the substrate. A second source/drain region is disposed at the other side of the T-shaped gate within the substrate. | 10-30-2008 |
| 20080283904 | TWO-BIT FLASH MEMORY CELL AND METHOD FOR MANUFACTURING THE SAME - A two-bit flash memory cell includes a substrate, a gate oxide layer disposed on the substrate, a gate stacked on the gate oxide layer. A charge storage spacer stack is disposed at either side of the gate. The charge storage spacer stack includes a bottom charge storage layer and an upper spacer layer. An insulating layer is disposed between the charge storage spacer stack and the gate. A liner is disposed underneath the bottom charge storage layer. A source/drain region is disposed at one side of the bottom charge storage layer within the substrate. | 11-20-2008 |
| 20090017604 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate. | 01-15-2009 |
| 20090020801 | TWO-BIT FLASH MEMORY CELL STRUCTURE AND METHOD OF MAKING THE SAME - A flash memory cell includes a control gate oxide layer on a substrate, a T-shaped control gate on the control gate oxide layer, a floating gate disposed on two recessed sidewalls of the T-shaped control gate, an insulating layer between the control gate and the floating gate, a dielectric layer between the floating gate and the substrate, a spacer on the sidewall of the floating gate, a P | 01-22-2009 |
| 20090090955 | ELEVATED CHANNEL FLASH DEVICE AND MANUFACTURING METHOD THEREOF - A FLASH device including a substrate having a protrusive portion integrally formed thereon, two floating gates, a control gate and a dielectric layer is provided. The two floating gates are disposed on two sides of the protrusive portion and respectively covering a portion of the protrusive portion. The control gate is disposed on top of the protrusive portion and sandwiched between the two floating gates. The dielectric layer is disposed between each of the two floating gates and the control gate. Because the control gate of the FLASH device is disposed on the protrusive portion, an elevated channel can be formed. Moreover, because of the position of the two floating gates, an effective floating gate (FG) length can be increased without impacting the cell density. | 04-09-2009 |
| 20090108321 | FLASH MEMORY - A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate. | 04-30-2009 |
| 20090114968 | RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME - A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness. | 05-07-2009 |
| 20090256189 | TWO BIT U-SHAPED MEMORY STRUCTURE AND METHOD OF MAKING THE SAME - A memory structure includes: a substrate; a control gate positioned on the substrate; floating gates positioned at two sides of the control gate, wherein the floating gates have a U-shaped bottom embedded in the substrate; a first dielectric layer positioned between the control gate and the substrate; a second dielectric layer positioned between the U-shaped bottom of the floating gates and the substrate; a third dielectric layer positioned between the control gate and the floating gates; a local doping region positioned around the floating gates channel; and a source/drain doping region positioned in the substrate at a side of the floating gates. | 10-15-2009 |
| 20090267126 | RECESS CHANNEL TRANSISTOR - A recess channel transistor includes a semiconductor substrate; a trench isolation region in the semiconductor substrate, which defines an active area; a gate trench in the active area, wherein the gate trench includes a round lower portion; a recessed gate embedded in the gate trench with a spherical gate portion situated in the round lower portion; a gate oxide layer in the round lower portion between the semiconductor substrate and the spherical gate portion; a source region in the active area at one side of the recessed gate; a drain region in the active area at the other side of the recessed gate; and a channel region between the source region and the drain region, wherein the channel region presents a convex curve profile when viewed from a channel widthwise direction. | 10-29-2009 |
