Patent application number | Description | Published |
20080251494 | Method for manufacturing circuit board - A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed. | 10-16-2008 |
20080264676 | Circuit board and method for manufaturing thereof - A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator. | 10-30-2008 |
20090011220 | Carrier and method for manufacturing printed circuit board - A carrier and a method for manufacturing a printed circuit board are disclosed. The method for manufacturing a printed circuit board may include: forming a first circuit pattern on each of a pair of release layers, which are attached respectively to either side of a base layer by adhesive layers; detaching the pair of release layers from the base layer; stacking and pressing the pair of release layers onto either side of an insulation substrate such that the first circuit patterns are buried in the insulation substrate; and separating the pair of release layers. By forming a circuit pattern on each of a pair of release layers with a single process, and transferring the circuit pattern into each side of an insulation substrate, the manufacturing process can be shortened and circuit patterns can be formed to a high density. | 01-08-2009 |
20090140429 | Metal interconnection of a semiconductor device and method of manufacturing the same - A method of manufacturing a metal interconnection of a semiconductor device includes forming a base layer with at least one groove, the at least one groove having an open upper portion, forming a first metal layer in the at least one groove, forming a seed metal layer on the first metal layer in the at least one groove, the seed metal layer being only on a bottom surface of the at least one groove, and forming a metal pattern grown from the seed metal layer to fill the at least one grove. | 06-04-2009 |
20100013094 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy. | 01-21-2010 |
20100018633 | METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom | 01-28-2010 |
20110226626 | APPARATUS AND METHOD FOR TREATING SUBSTRATE - A substrate treating device may include a plating treatment portion configured to perform a plating process of a substrate, a wet treatment portion configured to perform a wet treating process of the substrate, the wet treatment portion being under the plating treatment portion, and a substrate support portion configured to support the substrate so that a plating surface of the substrate faces upward, the substrate support portion being further configured to move the substrate between the plating treatment portion and the wet treatment portion. | 09-22-2011 |
20110259627 | Circuit board with buried circuit pattern - A circuit board includes: an insulator having a groove; a circuit layer filling a portion of the groove; a solder pad on the circuit layer filling the remainder of the groove; and a circuit pattern electrically connected with the circuit layer, the circuit pattern buried in the insulator such that a portion of the circuit pattern is exposed at a surface of the insulator. | 10-27-2011 |
20120086123 | SEMICONDUCTOR ASSEMBLY AND SEMICONDUCTOR PACKAGE INCLUDING A SOLDER CHANNEL - Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction. | 04-12-2012 |
20120111607 | CIRCUIT BOARD WITH HIGH-DENSITY CIRCUIT PATTERNS - A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein. | 05-10-2012 |
20120292195 | APPARATUS AND METHOD FOR ELECTROPLATING FOR SEMICONDUCTOR SUBSTRATE - An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution. | 11-22-2012 |
20120295434 | SOLDER COLLAPSE FREE BUMPING PROCESS OF SEMICONDUCTOR DEVICE - A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps. | 11-22-2012 |
20130000978 | Joint Structures Having Organic Preservative Films - The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof. | 01-03-2013 |
20130075905 | Semiconductor Chips and Semiconductor Packages and Methods of Fabricating the Same - A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer. | 03-28-2013 |
20130313707 | Electrical Interconnections of Semiconductor Devices and Methods for Fabricating the Same - Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad. | 11-28-2013 |
20130334656 | ELECTRICAL INTERCONNECTION STRUCTURES INCLUDING STRESS BUFFER LAYERS - Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening. | 12-19-2013 |
20150012671 | STORAGE SYSTEMS AND UFS SYSTEMS CONFIGURED TO CHANGE INTERFACE MODE IN ACTIVE STATE - A storage system includes a host and a storage device. The storage device includes a device controller and a device interface. The device controller is configured to generate interface idle time information in response to a command received from a host, the interface idle time information being determined based on an estimated time to execute at least one operation at the memory storage device. The device interface is configured to output the interface idle time information to the host. | 01-08-2015 |
20150032915 | STORAGE SYSTEM INCLUDING DATA TRANSFER SPEED MANAGER AND METHOD FOR CHANGING DATA TRANSFER SPEED THEREOF - A storage system according to an exemplary embodiment of the inventive concept includes a host and a storage device. The host includes a link speed table having data transfer speed information for an application. A data transfer speed manager is configured to calculate a predetermined transfer speed based on the data transfer speed information for the application. A device driver is configured to control an operation of the storage device. A host controller is configured to change a data transfer speed of an interface based on the predetermined transfer speed provided through the device driver. | 01-29-2015 |
20150048918 | COIL UNIT FOR THIN FILM INDUCTOR, MANUFACTURING METHOD OF COIL UNIT FOR THIN FILM INDUCTOR, THIN FILM INDUCTOR AND MANUFACTURING METHOD OF THIN FILM INDUCTOR - Embodiments of the invention provide a coil unit for a thin film inductor, a manufacturing method of a coil unit for a thin film inductor, a thin film inductor, and a manufacturing method of a thin film inductor. According to an embodiment, there is provided a coil unit for a thin film inductor. The coil unit includes an insulator having a dual insulating layer of different materials, and coil patterns respectively embedded in upper and lower surfaces of the insulator. The coil patterns include a coil pattern formed of a plurality of plating layers. | 02-19-2015 |