| Patent application number | Description | Published |
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| 20090156182 | System and method for generating a recommendation on a mobile device - A system and a method generate a recommendation on a mobile device. The system and the method may use a time, a location, a venue and/or an event to generate the recommendation. Further, the system and the method may use an event database to determine current interests of the user. Still further, the system and the method for generating a recommendation on a mobile device may use a transactional history of the user and/or behavior of other users to generate the recommendation. The system and the method may recommend, for example, digital media, news and event information, editorial content and/or physical or digital merchandise. As a result, the system and the method may generate a recommendation that corresponds to the current interests of the user. | 06-18-2009 |
| 20090157680 | System and method for creating metadata - A system and a method create metadata for media files. The metadata may be information relating to, based on and/or associated with the media files. The metadata of the media files may be searched by one or more terminals. An event database connectable to a terminal may use a location, a date and/or a time of creation of the media files to associate specific events with the media files. Further, the specific events may be used by the database to create keywords associated with the media files. As a result, the system and the method may organize and/or may provide searching for media files. A web page may be generated for an event that accumulates the media files related to the event. | 06-18-2009 |
| Patent application number | Description | Published |
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| 20080209095 | STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A MEMORY SYSTEM - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus. | 08-28-2008 |
| 20080215783 | STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict. | 09-04-2008 |
| 20080215832 | DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE - A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict. | 09-04-2008 |
| 20090150572 | STRUCTURE FOR HANDLING DATA REQUESTS - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. | 06-11-2009 |
| 20090150618 | STRUCTURE FOR HANDLING DATA ACCESS - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. | 06-11-2009 |
| Patent application number | Description | Published |
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| 20080244130 | FLOW LOOKAHEAD IN AN ORDERED SEMAPHORE MANAGEMENT SUBSYSTEM - In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order. | 10-02-2008 |
| 20090150401 | SYSTEM AND METHOD FOR HANDLING DATA ACCESS - A method for handling speculative access requests for a storage device in a computer system is provided. The method includes the steps of providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to be speculatively issued, and intermixing demand accesses and speculative accesses in accordance with the speculative access threshold. In another embodiment, a method for reducing data access latency experienced by a user in a computer network is provided. The method includes the steps of providing a web page comprising a link to a data file stored on a database connected to the computer network, selecting a speculative access threshold corresponding to a selected percentage of data accesses which are to be speculatively provided to the user, and speculatively providing the data file in accordance with the speculative access threshold. | 06-11-2009 |
| 20090150622 | SYSTEM AND METHOD FOR HANDLING DATA REQUESTS - A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold. | 06-11-2009 |
