| Patent application number | Description | Published |
|---|
| 20090103372 | HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS - The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications. | 04-23-2009 |
| 20090103373 | HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS - The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications. | 04-23-2009 |
| 20090103387 | HIGH PERFORMANCE HIGH CAPACITY MEMORY SYSTEMS - The present invention provides memory system architectures developed to increase the capacity of memory systems. Typically applications including the main memory of computers. Memory systems of the present invention can achieve capacities larger than prior art systems by one or two orders of magnitudes without significant degradation in performance while using system interfaces that are compatible with existing memory systems with no or minimal modifications. | 04-23-2009 |
| 20100002532 | ULTRA-LOW POWER HYBRID SUB-THRESHOLD CIRCUITS - The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. | 01-07-2010 |
| 20100026408 | SIGNAL TRANSFER FOR ULTRA-HIGH CAPACITY CIRCUITS - The present invention provides high performance, low power signal transfer methods for linking large numbers of integrated chips into ultra-high capacity circuits; Example application of the present invention including ultra-high capacity memory systems, and router systems. | 02-04-2010 |
| 20100231292 | ULTRA-LOW POWER HYBRID CIRCUITS - The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. Hybrid power saving mode for logic circuits provide significant power saving and fast recovery time without performance degradation. | 09-16-2010 |
| 20100237904 | High Performance Output Drivers and Anti-Reflection Circuits - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s). | 09-23-2010 |
| 20100327902 | Power saving termination circuits for dram modules - The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes significant less power relative to prior art termination resistors at low frequency and behave as a matching impedance at high frequency. Similar methods and structures are also applicable for PCIe, SATA, or MIPI differential interfaces. | 12-30-2010 |
| 20110089541 | Area reduction for electrical diode chips - Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes. | 04-21-2011 |
| 20110089542 | Area reduction for electrical diode chips - Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes. | 04-21-2011 |
| 20110089555 | AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS - Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. | 04-21-2011 |
| 20110089557 | Area reduction for die-scale surface mount package chips - Using side-wall conductor leads to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of die-scale surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. | 04-21-2011 |
| 20110115097 | AREA EFFICIENT THROUGH-HOLE CONNECTIONS - Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection. | 05-19-2011 |
| 20110133337 | AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS - Using side-wall conductor leads deposited on the side-walls of a base substrate to form package level conductor leads for active circuits manufactured on silicon substrate(s) stacked on the base substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. | 06-09-2011 |
| 20110133772 | High Performance Low Power Output Drivers - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces. | 06-09-2011 |
| 20110133773 | High Performance Output Drivers and Anti-Reflection Circuits - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s). | 06-09-2011 |
| 20110133780 | HIGH PERFORMANCE LOW POWER OUTPUT DRIVERS - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces. | 06-09-2011 |
