| Patent application number | Description | Published |
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| 20080224789 | PHASE LOCKED LOOP AND METHOD THEREOF - In a phase locked loop (PLL), phase shifters shift a phase of an input signal. Based on the phases of the input signal, the shifted signals, and a frequency division output signal, phase frequency detectors (PFDs) generate phase difference signals. In response to the phase difference signals, charge pumps (CPs) control output voltages thereof. Based on the output voltages of the CPs, a voltage controlled oscillator (VCO) outputs an output signal. A frequency divider divides the frequency of the output signal from the VCO to generate the frequency division output signal. A circulator outputs the frequency division output signal to one of the PFDs at a proper timing. A modulator reduces quantization errors of the frequency divider. | 09-18-2008 |
| 20090212868 | LOW POWER COMSUMPTION, LOW NOISE AND HIGH POWER GAIN DISTRIBUTED AMPLIFERS FOR COMMUNICATION SYSTEMS - Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed. | 08-27-2009 |
| Patent application number | Description | Published |
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| 20100171204 | THREE-DIMENSIONAL PACKAGE - A three-dimensional package includes a carrier, a first die mounted on a first surface of the carrier, and a second die stacked on the first die. The first die includes first bond pads and second bond pads juxtaposed in separate two rows within a central region of the first die. The package further includes first bond fingers disposed on the first surface along a first side of the carrier, and second bond fingers along a second side opposite to the first side. A first bond wire is bonded to one of the first bond pads and extends to one the first bond fingers. The first bond wire overlies the row of the second bond pads. A second bond wire is bonded to one of the second bond pads and extends to one the second bond fingers. The second bond wire overlies the row of the first bond pads. | 07-08-2010 |
| 20100171212 | SEMICONDUCTOR PACKAGE STRUCTURE WITH PROTECTION BAR - A semiconductor package structure includes a carrier, a chip or multi-chips mounted on a top surface of the carrier, a molding compound encapsulating the top surface and the chips, a plurality of solder balls distributed on a bottom surface of the carrier, and a protection bar formed of thermosetting plastic material formed on the bottom surface. | 07-08-2010 |
| 20110084374 | SEMICONDUCTOR PACKAGE WITH SECTIONED BONDING WIRE SCHEME - A semiconductor package includes a carrier substrate having thereon at least one bond finger; a semiconductor die mounted on a top surface of the carrier substrate; at least one active bond pad disposed on the semiconductor die; at least one dummy bond pad disposed on the semiconductor die; a first bonding wire extending between the at least one active bond pad and the at least one dummy bond pad; a second bonding wire extending between the at least one dummy bond pad and the at least one bond finger; and a molding compound encapsulating at least the semiconductor die. | 04-14-2011 |
| 20110086580 | WAFER BACK SIDE GRINDING PROCESS - A wafer back side grinding process. A workpiece comprising a first assembly having a first semiconductor wafer and a second assembly having a second semiconductor wafer is provided. A first back side of the first semiconductor wafer is grinded by using the second assembly as a carrier. Thereafter, a second back side of the second semiconductor wafer is grinded. | 04-14-2011 |
| 20110115067 | SEMICONDUCTOR CHIP PACKAGE WITH MOLD LOCKS - A semiconductor chip package includes a base comprising a die attach region and a mold-lock forming region surrounding the die attach region; a die mounted onto the base within the die attach region; a plurality of line-shaped trenches in the mold-lock forming region; a mold body encapsulating the die; and a mold lock inlaid in each of the line-shaped trenches to securely interlock the mold body to the base. | 05-19-2011 |
| 20110117232 | SEMICONDUCTOR CHIP PACKAGE WITH MOLD LOCKS - A semiconductor chip package is provided. A semiconductor chip package includes a base comprising a top surface and a bottom surface, the top surface comprising a die attach region and a through-hole forming region surrounding the die attach region, a die attached on the die attach region, a molding material encapsulating the die and a plurality of through holes filled up with the molding material formed in the through-hole forming region. | 05-19-2011 |
