Patent application number | Description | Published |
20100304042 | METHOD FOR FORMING SUPERHIGH STRESS LAYER - A method for forming super high stress layer is provided. First, a substrate is provided. Second, an ammonia-related pretreatment is performed on the substrate. The flow rate of ammonia is not less than s.c.c.m. and the high-frequency source power is set to be not less than 800 W. Later, the super high stress layer is formed on the substrate having undergone the ammonia-related pretreatment. | 12-02-2010 |
20110065245 | METHOD FOR FABRICATING MOS TRANSISTOR - A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate and a source/drain region in the semiconductor substrate adjacent to two sides of the gate structure; covering a stress layer on the gate structure and the source/drain region; etching away the stress layer to form a plurality of openings with larger top and smaller bottom to expose surface of the gate structure and the source/drain region; forming a metal layer in the openings; and using the stress layer as a salicide block to react the metal layer with the gate structure and the source/drain region for forming a plurality of silicide layers. | 03-17-2011 |
20110169095 | STRAINED-SILICON TRANSISTOR AND METHOD OF MAKING THE SAME - A structure of a strained-silicon transistor includes a PMOS disposed on a substrate, a silicon nitride layer positioned on the PMOS, and a compressive stress film disposed on the silicon nitride layer, wherein the silicon nitride has a stress between −0.1 Gpa and −3.2 Gpa, and the stress of the silicon nitride is smaller than the stress of the compressive stress layer. | 07-14-2011 |
20120071004 | STRESS-ADJUSTING METHOD OF MOS DEVICE - A stress-adjusting method for use in a manufacturing system of a MOS device is provided. At first, a first stress layer is formed onto a substrate wherein at least two MOSFETs are previously formed on the substrate. The first stress layer overlies an inter-gate region between two adjacent gate regions of the MOSFETs and overlies the two adjacent gate regions. Then, the first stress layer in the inter-gate region is thinned. A second stress layer is further formed onto the substrate to overlie the thinned first stress layer in the inter-gate region to provide the resulting MOS device with satisfactory stress. | 03-22-2012 |
20120326238 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region thereon; forming a high-k dielectric layer, a barrier layer, and a first metal layer on the substrate; removing the first metal layer of the second region; forming a polysilicon layer to cover the first metal layer of the first region and the barrier layer of the second region; patterning the polysilicon layer, the first metal layer, the barrier layer, and the high-k dielectric layer to form a first gate structure and a second gate structure in the first region and the second region; and forming a source/drain in the substrate adjacent to two sides of the first gate structure and the second gate structure. | 12-27-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130020657 | METAL OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a MOS transistor is provided. A substrate has a high-k dielectric layer and a barrier in each of a first opening and a second opening formed by removing a dummy gate and located in a first transistor region and a second transistor region. A dielectric barrier layer is formed on the substrate and filled into the first opening and the second opening to cover the barrier layers. A portion of the dielectric barrier in the first transistor region is removed. A first work function metal layer is formed. The first work function metal layer and a portion of the dielectric barrier layer in the second transistor region are removed. A second work function metal layer is formed. The method can avoid a loss of the high-k dielectric layer to maintain the reliability of a gate structure, thereby improving the performance of the MOS transistor. | 01-24-2013 |
20130334650 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 12-19-2013 |
20140035070 | METAL OXIDE SEMICONDUCTOR TRANSISTOR - A MOS transistor including a silicon substrate, a first gate structure and a second gate structure disposed on the silicon substrate is provided. The first gate structure and the second gate structure each includes a high-k dielectric layer disposed on the silicon substrate, a barrier layer disposed on the high-k dielectric layer, and a work function layer disposed on and contacted with the barrier layer. The MOS transistor further includes a dielectric material spacer. The dielectric material spacer is disposed on the barrier layer of each of the first gate structure and the second gate structure and surrounding the work function layer of each of the first gate structure and the second gate structure. | 02-06-2014 |
20140042501 | MOS TRANSISTOR AND PROCESS THEREOF - A MOS transistor includes a gate structure and a spacer. The gate structure is located on a substrate. The spacer is located on the substrate beside the gate structure, and the spacer includes an L-shaped inner spacer and an outer spacer, wherein the outer spacer is located on the L-shaped inner spacer, and the two ends of the L-shaped inner spacer protrude from the outer spacer. Moreover, the present invention also provides a MOS transistor process for forming the MOS transistor. | 02-13-2014 |
20140091395 | TRANSISTOR - A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer. | 04-03-2014 |
20140134824 | METHOD OF FABRICATING DIELECTRIC LAYER AND SHALLOW TRENCH ISOLATION - A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma. | 05-15-2014 |
20140199836 | METHOD FOR FORMING INTERLEVEL DIELECTRIC (ILD) LAYER - A method for forming an interlevel dielectric (ILD) layer includes the following steps. A MOS transistor on a substrate is provided. A first undoped oxide layer is deposited to cover the substrate and the MOS transistor. The first undoped oxide layer is planarized. A phosphorus containing oxide layer is deposited on the first undoped oxide layer. A second undoped oxide layer is deposited on the phosphorus containing oxide layer. | 07-17-2014 |
20140213034 | METHOD FOR FORMING ISOLATION STRUCTURE - A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material. | 07-31-2014 |
20140256115 | SEMICONDUCTOR PROCESS - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 09-11-2014 |
20150048486 | SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening. | 02-19-2015 |
20150087126 | METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS - A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer. | 03-26-2015 |