Patent application number | Description | Published |
20080219067 | INDIVIDUAL I/O MODULATION IN MEMORY DEVICES - A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster. | 09-11-2008 |
20080246520 | DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY - A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock path delay of the DLL system. The measure shot device is configured to provide a calibration sequence into the DLL loop and to detect the calibration sequence after the calibration sequence has passed through the DLL loop. The measure shot device is further configured to count the number of clocks for a period of time between providing and detecting the calibration sequence. The number of clocks can be used to calibrate components of the DLL system. | 10-09-2008 |
20080258785 | Periodic signal synchronization apparatus, systems, and methods - Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed. | 10-23-2008 |
20090052268 | SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path. | 02-26-2009 |
20090146712 | DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY - A delayed locked loop (DLL) system and method for determining a forward clock path delay are disclosed. One embodiment of the DLL system includes a delay line having a plurality of delay stages. The DLL system also includes a measure shot device configured to determine a forward clock path delay of the DLL system. The measure shot device is configured to provide a calibration sequence into the DLL loop and to detect the calibration sequence after the calibration sequence has passed through the DLL loop. The measure shot device is further configured to count the number of clocks for a period of time between providing and detecting the calibration sequence. The number of clocks can be used to calibrate components of the DLL system. | 06-11-2009 |
20090238012 | CONTROLLING SLEW RATE PERFORMANCE ACROSS DIFFERENT OUTPUT DRIVER IMPEDANCES - Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength of an output driver and configuring the pre-driver based on the determined output driver strength. | 09-24-2009 |
20090296512 | Apparatus for writing to mutiple banks of a memory device - In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number of banks between one and all banks. In addition, the method retains the discrete nature of the selected banks by allowing any row in each bank to be accessed regardless of the rows activated in other banks. As a result, rows of different memory banks that are intended to store similar data may be accessed simultaneously for purposes of writing the data in test and non-test modes. This allows for quicker writing to the SDRAM without the errors that may be created by other fast writing modes, such as data compression. | 12-03-2009 |
20100110813 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 05-06-2010 |
20100142287 | SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path. | 06-10-2010 |
20100250874 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 09-30-2010 |
20110001528 | PERIODIC SIGNAL SYNCHRONIZATION APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a phase difference between the output signal and the input signal, and to adjust a phase of the output signal based on the samples of the phase difference. Additional apparatus, systems, and methods are disclosed. | 01-06-2011 |
20110026345 | PRECHARGE CONTROL CIRCUITS AND METHODS FOR MEMORY HAVING BUFFERED WRITE COMMANDS - Memories, precharge control circuits, methods of controlling, and methods of utilizing are disclosed, including precharge control circuits for a memory having at least one bank of memory. One such control circuit includes at least one precharge preprocessor circuit. The precharge preprocessor circuit is coupled to a respective bank of memory and is configured to prevent precharge of the respective bank of memory until after execution of buffered write commands issued to the respective bank of memory is completed. | 02-03-2011 |
20120232716 | SYSTEM AND METHOD FOR PROVIDING TEMPERATURE DATA FROM A MEMORY DEVICE HAVING A TEMPERATURE SENSOR - A circuit and method for providing temperature data indicative of a temperature measured by a temperature sensor. The circuit is coupled to the temperature sensor and configured to identify for a coarse temperature range one of a plurality of fine temperature ranges corresponding to the temperature measured by the temperature sensor and generate temperature data that is provided on an asynchronous output data path. | 09-13-2012 |
20120246434 | SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE - A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state. | 09-27-2012 |
20120324179 | APPARATUS AND METHOD FOR BUFFERED WRITE COMMANDS IN A MEMORY - Memories, buffered write command circuits, and methods for executing memory commands in a memory. In some embodiments, read commands that are received after write commands are executed internally prior to executing the earlier received write commands. Write commands are buffered so that the commands can be executed upon completion of the later received read command. One example of a buffered write command circuit includes a write command buffer to buffer write commands and propagate buffered write commands therethrough in response to a clock signal and further includes write command buffer logic. The write command buffer logic generates an active clock signal to propagate the buffered write commands through the write command buffer for execution, suspends the active clock signal in response to receiving a read command after the write command is received, and restarts the active clock upon completion of the later received read command. | 12-20-2012 |
20140108877 | BOUNDARY SCAN TEST INTERFACE CIRCUIT - The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module. | 04-17-2014 |
20140153350 | METHODS AND APPARATUSES FOR REFRESHING MEMORY - Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method further includes refreshing the memory at a first refresh rate after receiving the self refresh command. The method further includes refreshing the memory at a second refresh rate in response to a determination that each memory cell of the memory has been refreshed at the first refresh rate. The first refresh rate is greater than a second refresh rate. | 06-05-2014 |
20140198591 | APPARATUSES AND METHODS FOR CONTROLLING A CLOCK SIGNAL PROVIDED TO A CLOCK TREE - Apparatuses, sense circuits, and methods for controlling a clock signal to a clock tree is described. An example apparatus includes a consecutive write command detection circuit configured to detect whether a next write command is received within a consecutive write command period of a current write command responsive to the current write command provided at an output of the write command register. The example apparatus further includes a clock signal control circuit coupled to the consecutive write command detection circuit and configured to control a clock signal to an input/output (I/O) latch based on whether the consecutive write command detection circuit detects that the next write command is within the consecutive write command period. | 07-17-2014 |
20140219043 | APPARATUSES AND METHODS FOR TARGETED REFRESHING OF MEMORY - Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory. | 08-07-2014 |
20150067197 | DATA PATTERN GENERATION FOR I/O TRAINING AND CHARACTERIZATION - A memory structure that can perform characterization of output data paths without accessing the main memory array includes: a plurality of output data paths; a plurality of registers coupled to the output data paths. The registers include: at least a first pattern register and a second pattern register, for respectively storing a first data pattern and a second data pattern; and at least a first mapping register, for storing a plurality of binary values, wherein each binary value indicates whether the first data pattern or the second data pattern should be mapped to a corresponding output data path. | 03-05-2015 |