| Patent application number | Description | Published |
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| 20080224259 | METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE - Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing. | 09-18-2008 |
| 20080244904 | Contour Structures to Highlight Inspection Regions - An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark. | 10-09-2008 |
| 20080254630 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect. | 10-16-2008 |
| 20080261393 | REDUCING WIRE EROSION DURING DAMASCENE PROCESSING - A damascene process incorporating a GCIB step is provided. The GCIB step can replace one or more CMP steps in the traditional damascene process. The GCIB step allows for selectable removal of unwanted material and thus, reduces unwanted erosion of certain nearby structures during damascene process. A GCIB step may also be incorporated in the damascene process as a final polish step to clean up surfaces that have been planarized using a CMP step. | 10-23-2008 |
| 20090001427 | CHARGE CARRIER BARRIER FOR IMAGE SENSOR - A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell. | 01-01-2009 |
| 20090045502 | CHIP SCALE PACKAGE WITH THROUGH-VIAS THAT ARE SELECTIVELY ISOLATED OR CONNECTED TO THE SUBSTRATE - A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate. | 02-19-2009 |
| 20090057908 | WIRE BOND PADS - A wire bond pad and method of fabricating the wire bond pad. The method including: providing a substrate; forming an electrically conductive layer on a top surface of the substrate; patterning the conductive layer into a plurality of wire bond pads spaced apart; and forming a protective dielectric layer on the top surface of the substrate in spaces between adjacent wire bond pads, top surfaces of the dielectric layer in the spaces coplanar with coplanar top surfaces of the wire bond pads. | 03-05-2009 |
| 20090085152 | THREE DIMENSIONAL VERTICAL E-FUSE STRUCTURES AND METHODS OF MANUFACTURING THE SAME - Three dimensional vertical e-fuse structures and methods of manufacturing the same are provided herein. The method of forming a fuse structure comprises providing a substrate including an insulator layer and forming an opening in the insulator layer. The method further comprises forming a conductive layer along a sidewall of the opening and filling the opening with an insulator material. The vertical e-fuse structure comprises a first contact layer and a second contact layer. The structure further includes a conductive material lined within a via and in electrical contact with the first contact layer and the second contact layer. The conductive material has an increased resistance as a current is applied thereto. | 04-02-2009 |
| 20090090983 | DUAL WORK FUNCTION HIGH VOLTAGE DEVICES - A transistor has a substrate having a channel region and source and drain regions within the substrate on opposite sides of the channel region. The structure includes a gate oxide above the channel region of the substrate and a gate conductor above the gate oxide. The polysilicon gate conductor comprises a source side positioned toward the source and a drain side positioned toward the drain. The source side comprises a first concentration of conductive doping and the drain side comprises a second concentration of the conductive doping that is less than the first concentration. | 04-09-2009 |
| 20090108347 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE - A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance. | 04-30-2009 |
| 20090124047 | STACKED IMAGE METHOD - An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light. | 05-14-2009 |
| 20090127710 | UNDERCUT-FREE BLM PROCESS FOR PB-FREE AND PB-REDUCED C4 - A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer of the barrier metal stack removed by etching. The diffusion barrier and C4 solder bump may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced. | 05-21-2009 |
| 20090140343 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE - A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation. | 06-04-2009 |
| 20090189286 | FINE PITCH SOLDER BUMP STRUCTURE WITH BUILT-IN STRESS BUFFER - A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing. | 07-30-2009 |
| 20090193378 | MODIFYING LAYOUT OF IC BASED ON FUNCTION OF INTERCONNECT AND RELATED CIRCUIT AND DESIGN STRUCTURE - Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect. | 07-30-2009 |
| 20090200663 | POLYMER AND SOLDER PILLARS FOR CONNECTING CHIP AND CARRIER - A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars. | 08-13-2009 |
| 20090224349 | IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS - An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels. | 09-10-2009 |
| 20090230547 | DESIGN STRUCTURE, SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE AND PACKAGING THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided. | 09-17-2009 |
| 20090235212 | DESIGN STRUCTURE, FAILURE ANALYSIS TOOL AND METHOD OF DETERMINING WHITE BUMP LOCATION USING FAILURE ANALYSIS TOOL - A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip. | 09-17-2009 |
| 20090242948 | METHOD OF FORMING AN INVERTED LENS IN A SEMICONDUCTOR STRUCTURE - A flat-top convex-bottom lower lens is formed by first applying a positive tone photoresist over a silicon oxide layer and an optional metallic barrier layer thereupon in a back-end-of-line (BEOL) metallization structure. The positive tone photoresist is exposed under defocused illumination conditions and/or employing a half-tone mask so that a cross-sectional profile of the positive tone photoresist after exposure contains a continuous and smooth concave profile, which is transferred into the underlying silicon oxide layer to form a concave cavity therein. After removing the photoresist, the cavity is filled with a high refractive index material such as silicon nitride, and planarized to form a flat-top convex-bottom lower lens. Various aluminum metal structures, a color filter, and a convex-top flat-bottom upper lens are thereafter formed so that the upper lens and the lower lens constitute a composite lens system. | 10-01-2009 |
| 20090250733 | PIXEL SENSOR WITH REDUCED IMAGE LAG - A tensile-stress-generating structure is formed above a gate electrode in a CMOS image sensor to apply a normal tensile stress between a charge collection well of a photodiode, which is also a source region of a transfer transistor, and a floating drain in the direction connecting the source region and the floating drain. The tensile stress lowers the potential barrier between the source region and the body of the transfer transistor to effect a faster and more through transfer of the electrical charges in the source region to the floating drain. Image lag is thus reduced in the CMOS image sensor. Further, charge capacity of the source region is also enhanced due to the normal tensile stress applied to the source region. | 10-08-2009 |
| 20090261426 | LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE - A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes. | 10-22-2009 |
| 20090273081 | PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR Pb-FREE C4 INTEGRATED CIRCUIT CHIP JOINING - A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls. | 11-05-2009 |
| 20090280631 | Electroless Metal Deposition For Dual Work Function - The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate. | 11-12-2009 |
| 20090283807 | Anti-Reflection Structures For CMOS Image Sensors - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 11-19-2009 |
| 20090286346 | Methods For Forming Anti-Reflection Structures For CMOS Image Sensors - Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection. | 11-19-2009 |
| 20090294812 | Optical Sensor Including Stacked Photosensitive Diodes - A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes. | 12-03-2009 |
| 20090294813 | Optical Sensor Including Stacked Photodiodes - A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes. | 12-03-2009 |
| 20090294901 | STRUCTURE AND METHOD OF FORMING ELECTRICALLY BLOWN METAL FUSES FOR INTEGRATED CIRCUITS - A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer. | 12-03-2009 |
| 20090302406 | DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS - A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures. | 12-10-2009 |
| 20090303366 | INTERLEVEL CONDUCTIVE LIGHT SHIELD - A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain. | 12-10-2009 |
| 20090305499 | INTRALEVEL CONDUCTIVE LIGHT SHIELD - A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield. | 12-10-2009 |
| 20100021656 | LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION - An interconnect structure which includes a metal-containing cap located atop each conductive feature that is present within a dielectric material is provided in which a surface region of the metal-containing cap is oxidized prior to the subsequent deposition of any other dielectric material thereon. Moreover, metal particles that are located on the surface of the dielectric material between the conductive features are also oxidized at the same time as the surface region of the metal-containing cap. This provides a structure having a reduced leakage current. In accordance with the present invention, the oxidation step is performed after electroless plating of the metal-containing cap and prior to the deposition of a dielectric capping layer or an overlying interlayer or intralevel dielectric material. | 01-28-2010 |
| 20100032835 | COMBINATION VIA AND PAD STRUCTURE FOR IMPROVED SOLDER BUMP ELECTROMIGRATION CHARACTERISTICS - The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in solder bumps and related structures. A semiconductor structure includes a wire comprising first and second wire segments, a pad formed over the wire, and a ball limiting metallization (BLM) layer formed over the pad. The semiconductor structure also includes a solder bump formed over the BLM layer, a terminal via formed over the BLM layer, and at least one peripheral via formed between the second wire segment and the pad. The first and second wire segments are discrete wire segments. | 02-11-2010 |
| 20100038773 | BOND PAD FOR WAFER AND PACKAGE FOR CMOS IMAGER - An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seat between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads. | 02-18-2010 |
| 20100038780 | UNDERFILL FLOW GUIDE STRUCTURES AND METHOD OF USING SAME - Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes. | 02-18-2010 |
| 20100052172 | METHOD OF FABRICATING COPPER DAMASCENE AND DUAL DAMASCENE INTERCONNECT WIRING - An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer. | 03-04-2010 |
| 20100065965 | METHODS OF FORMING SOLDER CONNECTIONS AND STRUCTURE THEREOF - A method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts. | 03-18-2010 |
| 20100155893 | Method for Forming Thin Film Resistor and Terminal Bond Pad Simultaneously - Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires. | 06-24-2010 |
| 20100155932 | BONDED SEMICONDUCTOR SUBSTRATE INCLUDING A COOLING MECHANISM - A bonded substrate comprising two semiconductor substrates is provided. Each semiconductor substrate includes semiconductor devices. At least one through substrate via is provided between the two semiconductor substrates to provide a signal path therebetween. The bottom sides of the two semiconductor substrate are bonded by at least one bonding material layer that contains a cooling mechanism. In one embodiment, the cooling mechanism is a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. In another embodiment, the cooling mechanism is a conductive cooling fin with two end portions and a contiguous path therebetween. The cooling fin is connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. | 06-24-2010 |
| 20100163949 | VERTICAL METAL-INSULATOR-METAL (MIM) CAPACITOR USING GATE STACK, GATE SPACER AND CONTACT VIA - A semiconductor structure including a vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. | 07-01-2010 |
| 20100164096 | Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a via formed in a dielectric layer to expose a contact pad and a capture pad formed in the via and over the dielectric layer. The capture pad has openings over the dielectric layer to form segmented features. The solder bump is deposited on the capture pad and the openings over the dielectric layer. | 07-01-2010 |
| 20100164104 | Structures and Methods for Improving Solder Bump Connections in Semiconductor Devices - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands. | 07-01-2010 |
| 20100167522 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands. | 07-01-2010 |
| 20100230729 | PIXEL SENSOR CELL INCLUDING LIGHT SHIELD - CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate | 09-16-2010 |
| 20100258900 | ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING - An apparatus comprises a first layer within a semiconductor chip having active structures electrically connected to other active structures and having electrically isolated first inactive structures. A second layer within the semiconductor chip is physically connected to the first layer. The second layer comprises an insulator and has second inactive structures. The first inactive structures are physically aligned with the second inactive structures. | 10-14-2010 |
| 20100261335 | PROCESS FOR WET SINGULATION USING A DICING MOAT STRUCTURE - A method includes receiving at least one wafer having a front side and a backside, where the front side has a plurality of integrated circuit chips thereon. The backside of the wafer is thinned, a pattern of material is removed from the backside of the wafer to form a plurality of dicing trenches. Each of the dicing trenches are positioned opposite a location on the front side of the wafer that corresponds to edges of each of the plurality of chips. The dicing trenches are filled with a filler material and a dicing support is attached to a front side of the wafer. The filler material is removed from the dicing trenches, and a force is applied to the dicing support to separate each of the plurality of chips on the wafer from each other along the dicing trenches. | 10-14-2010 |
| 20100261351 | Spacer Linewidth Control - A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step. | 10-14-2010 |
| 20100264473 | ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS - Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package. | 10-21-2010 |
| 20110006422 | Structures and methods to improve lead-free C4 interconnect reliability - Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer. | 01-13-2011 |
| 20110018091 | FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE - A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse. | 01-27-2011 |
| 20110031616 | STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES - Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands. | 02-10-2011 |
| 20110042779 | FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE - A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, fanning an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse. | 02-24-2011 |
| 20110042826 | SACRIFICIAL INORGANIC POLYMER INTERMETAL DIELECTRIC DAMASCENE WIRE AND VIA LINER - The present invention provides a method of forming a rigid interconnect structure, and the device therefrom, including the steps of providing a lower metal wiring layer having first metal lines positioned within a lower low-k dielectric; depositing an upper low-k dielectric atop the lower metal wiring layer; etching at least one portion of the upper low-k dielectric to provide at least one via to the first metal lines; forming rigid dielectric sidewall spacers in at least one via of the upper low-k dielectric; and forming second metal lines in at least one portion of the upper low-k dielectric. The rigid dielectric sidewall spacers may comprise of SiCH, SiC, SiNH, SiN, or SiO | 02-24-2011 |
| 20110045644 | FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE - A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse. | 02-24-2011 |
| 20110072409 | OPTICAL SENSOR INCLUDING STACKED PHOTODIODES - A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes. | 03-24-2011 |
| 20110079827 | STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION - A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench. | 04-07-2011 |
| 20110092056 | ELECTRICALLY CONDUCTIVE PATH FORMING BELOW BARRIER OXIDE LAYER AND INTEGRATED CIRCUIT - Methods of forming an electrically conductive path under a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate and an integrated circuit including the path are disclosed. In one embodiment, the method includes forming an electrically conductive path below a barrier oxide layer of a semiconductor-on-insulator (SOI) substrate, the method comprising: forming a first barrier oxide layer on a semiconductor substrate; forming the electrically conductive path within the first barrier oxide layer; and forming a second barrier oxide layer on the first barrier oxide layer. The electrically conductive path allows reduction of SRAM area by forming a wiring path underneath the barrier oxide layer on the SOI substrate. | 04-21-2011 |
| 20110098838 | SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS - Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized. | 04-28-2011 |
| 20110111590 | DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES - Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects. | 05-12-2011 |
| 20110129955 | DELAMINATION AND CRACK RESISTANT IMAGE SENSOR STRUCTURES AND METHODS - A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures. | 06-02-2011 |
| 20110133307 | DAMAGE PROPAGATION BARRIER - A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure. | 06-09-2011 |
| 20110134504 | Micro-Electro-Mechanical System Tiltable Lens - A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided. | 06-09-2011 |
| 20110140271 | INTEGRATED CIRCUIT CHIP WITH PYRAMID OR CONE-SHAPED CONDUCTIVE PADS FOR FLEXIBLE C4 CONNECTIONS AND A METHOD OF FORMING THE INTEGRATED CIRCUIT CHIP - Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip. | 06-16-2011 |
