| Patent application number | Description | Published |
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| 20090244501 | APPARATUS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK - An apparatus for real-time contamination, environmental, or physical monitoring of a photomask. The apparatus includes a photomask having a patterned region configured to correspond to features of an integrated circuit and a sensor physically coupled with the photomask. The sensor is configured to monitor an attribute related to the photomask. Attributes monitored by the sensor may include chemical contamination, temperature changes, humidity changes, acceleration, shock, vibration, optical flux through the photomask, electrostatic discharge environment of the photomask, particulates, and pressure. | 10-01-2009 |
| 20090267178 | DEVICE STRUCTURES FOR ACTIVE DEVICES FABRICATED USING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT - Device structure for active devices fabricated in a semiconductor-on-insulator (SOI) substrate and design structures for a radiofrequency integrated circuit. The device structure includes a first isolation region in the semiconductor layer that extends from a top surface of a semiconductor layer to a first depth, a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth, and a first doped region in the semiconductor layer. The first doped region is disposed vertically between the first isolation region and an insulating layer disposed between the semiconductor layer and a handle wafer of the SOI substrate. The device structure may be included in a design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. | 10-29-2009 |
| 20090269903 | METHODS FOR FABRICATING ACTIVE DEVICES ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE UTILIZING MULTIPLE DEPTH SHALLOW TRENCH ISOLATIONS - Methods for fabricating a device structure in a semiconductor-on-insulator substrate. The method includes forming a first isolation region in the substrate device layer that extends from a top surface of the device layer to a first depth and forming a second isolation region in the semiconductor layer that extends from the top surface of the semiconductor layer to a second depth greater than the first depth. The method further includes forming a doped region of the device structure in the semiconductor layer that is located vertically between the first isolation region and the insulating layer. | 10-29-2009 |
| 20090278185 | DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY - Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode. | 11-12-2009 |
| 20090280607 | METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY - Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body. | 11-12-2009 |
| 20090319973 | SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION - A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip. | 12-24-2009 |
| 20100029021 | METHODS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK - Methods for real-time contamination, environmental, or physical monitoring of a photomask. An attribute of a photomask is monitored using a sensor of an electronics package attached to the photomask. The methods further include generating one or more sensor signals relating to the monitored attribute with the sensor and transmitting the one or more sensor signals from the electronics package to a control system. | 02-04-2010 |
| 20100031223 | SYSTEMS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK - Systems for real-time contamination, environmental, or physical monitoring of a photomask. The system includes an electronics package physically mounted to the photomask and a processing device in communication with the electronics package. The electronics package includes a sensor configured to monitor the attribute and generate sensor data. The processing device is configured to analyze the sensor data communicated from the electronics package to the processing device. | 02-04-2010 |
| 20100038754 | Back-End-of-Line Resistive Semiconductor Structures - In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines. | 02-18-2010 |
| 20100041202 | Methods For Forming Back-End-Of-Line Resistive Semiconductor Structures - In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines. | 02-18-2010 |
| 20100162196 | STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS - A photomask, method of designing, of fabricating, of designing, a method of inspecting and a system for designing the photomask. The photomask, includes: a cell region, the cell region comprising one or more chip regions, each chip region comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit chip and one or more kerf regions, each kerf region comprising a pattern of opaque and clear sub-regions corresponding to features of an integrated circuit kerf; a clear region formed adjacent to a side of a copy region, the copy region comprising opaque and clear sub-regions that are copies of at least a part of the cell region; and an opaque region between the clear region and the cell region. | 06-24-2010 |
| 20100164013 | RANDOM PERSONALIZATION OF CHIPS DURING FABRICATION - Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc. | 07-01-2010 |
| 20100190096 | TARGET AND METHOD FOR MASK-TO-WAFER CD, PATTERN PLACEMENT AND OVERLAY MEASUREMENT AND CONTROL - A method for mask-to-wafer correlation among multiple masking levels of a semiconductor manufacturing process. The method includes creating compact targets containing structure patterns suitable for pattern placement, critical dimension and overlay measurement at a set of common locations on two or more patterning layers, and creating at least two masks containing functional circuit structure patterns and the compact targets at locations between functional circuit structure patterns. The method then includes measuring the targets, determining overlay variation between the masks, exposing and creating with one mask a first lithographic processing layer on a wafer, and exposing and creating with another mask a second lithographic processing layer on the wafer, over the first layer. The method further includes measuring the targets on the wafer at one or more of the layers, and correlating the mask and wafer measurements to distinguish mask and lithography induced components of critical dimension and overlay variation. | 07-29-2010 |
| 20100230732 | FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC - A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane. | 09-16-2010 |
| 20100261351 | Spacer Linewidth Control - A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step. | 10-14-2010 |
| 20110073985 | Method of Generating Uniformly Aligned Well and Isolation Regions in a Substrate and Resulting Structure - A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region. | 03-31-2011 |
| 20110098838 | SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS - Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized. | 04-28-2011 |
| 20110134504 | Micro-Electro-Mechanical System Tiltable Lens - A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided. | 06-09-2011 |
| 20110165502 | METHOD AND SYSTEM FOR FEATURE FUNCTION AWARE PRIORITY PRINTING - A method and system for photomask pattern generation is provided, and more specifically, a method and system for feature function aware priority printing is provided. The method of printing a photolithographic mask includes fracturing mask design data into write shapes that are multiples of a spot size and passing fractured mask design data to a write tool. Additionally, the method includes writing one or more non-critical shapes according to one or more time-saving rules. | 07-07-2011 |
