Patent application number | Description | Published |
20080275585 | EXTRACTION OF KEY PROCESS PARAMETER - A system, method, and computer readable medium for extracting a key process parameter correlative to a selected device parameter are provided. In an embodiment, the key process parameter is determined using a gene map analysis. The gene map analysis includes grouping highly correlative process parameter and determining the correlation of a group to the selected device parameter. In an embodiment, the groups having greatest correlation to the selected device parameter are displayed in a correlation matrix and/or a gene map. | 11-06-2008 |
20080275586 | Novel Methodology To Realize Automatic Virtual Metrology - A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology. | 11-06-2008 |
20080275588 | PREDICTION OF UNIFORMITY OF A WAFER - A method of monitoring uniformity of a wafer is provided. A wafer parameter is selected. Manufacturing data is collected. The manufacturing data includes measurements of the selected wafer parameter. An average offset profile of the wafer parameter for a first and second wafer is determined using the manufacturing data. The first and second wafer are associated with a product type and were processed by a processing tool. An offset profile for a third wafer is predicted for a wafer using the average offset profile. The third wafer is associated with the product type and was processed by the processing tool. | 11-06-2008 |
20080275676 | METHODOLOGY TO ENABLE WAFER RESULT PREDICTION OF BATCH TOOLS - A method to enable wafer result prediction from a batch processing tool, includes collecting manufacturing data from a batch of wafers processed in batch in the batch processing tool, to form a batch processing result; defining a degree of freedom of the batch processing result based on the manufacturing data; and performing an optimal curve fitting by trial and error for an optimal function model of the batch processing result based on the batch processing result. | 11-06-2008 |
20080295412 | APPARATUS FOR STORING SUBSTRATES - An apparatus includes an enclosure and a door configured to seal the enclosure. The door includes a plate. A rotational apparatus is disposed over the plate. At least one first member with a first arm extends from a first rib of the first member. At least one second member with a second arm extends from a second rib of the second member. The first and second arms are connected to the rotational apparatus. At least one corner member has a first edge. The first edge has a shape corresponding to a shape of a corner of the frame. The corner member is connected to a first end of the third arm. A second end of the third arm is connected to the rotational apparatus. A sealing material is disposed along a first longitudinal side of the first rib and a second longitudinal side of the second rib. | 12-04-2008 |
20080298933 | SUBSTRATE CARRIER, PORT APPARATUS AND FACILITY INTERFACE AND APPARATUS INCLUDING SAME - An apparatus includes a first enclosure, a first door, at least one first valve, at least one inlet diffuser and at least one substrate holder. The first enclosure has a first opening. The first door is configured to seal the first opening. The first valve is coupled to the first enclosure. The inlet diffuser is coupled to the first valve and configured to provide a first gas with a temperature substantially higher than a temperature of an environment around the first enclosure. Each substrate holder disposed within the first enclosure supports at least one substrate. | 12-04-2008 |
20080304944 | Preventing Contamination in Integrated Circuit Manufacturing Lines - A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof. | 12-11-2008 |
20090035883 | Auto Routing for Optimal Uniformity Control - A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools. | 02-05-2009 |
20090142860 | SYSTEM AND METHOD FOR ENHANCED CONTROL OF COPPER TRENCH SHEET RESISTANCE UNIFORMITY - A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches. | 06-04-2009 |
20090142903 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 06-04-2009 |
20090317214 | NOVEL WAFER'S AMBIANCE CONTROL - A semiconductor manufacturing system, an interface system, a carrier, and a method for providing an ambient controlled environment is disclosed. The semiconductor manufacturing system comprises a plurality of process chambers; at least one interface system, wherein the interface system includes a first ambient control element; at least one carrier, wherein the carrier comprises a second ambient control element; and a control module coupled to the plurality of process chambers, the at least one interface system, and the at least one carrier. | 12-24-2009 |
20100015894 | CMP by Controlling Polish Temperature - A method for manufacturing integrated circuits on a wafer includes providing a facility-supplied room temperature solution; controlling the temperature of the facility-supplied room temperature solution to a desired temperature set point to generate a rinse solution; and rinsing a polishing pad using the rinse solution. The wafer is then polished by means of a chemical mechanical polishing process. | 01-21-2010 |
20100285723 | POLISHING APPARATUS - A chemical mechanical polishing (CMP) device for processing a wafer is provided which includes a plate for supporting the wafer to be processed in a face-up orientation, a polishing head opposing the plate, wherein the polishing head includes a rotatable polishing pad operable to contact the wafer while the polishing pad is rotating, and a slurry coating system providing a slurry to the polishing pad for polishing the wafer. | 11-11-2010 |
20100327463 | STACKED STRUCTURES AND METHODS OF FABRICATING STACKED STRUCTURES - A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure. | 12-30-2010 |
20110009998 | Near Non-Adaptive Virtual Metrology and Chamber Control - Embodiments of the present invention relate to a method for a near non-adaptive virtual metrology for wafer processing control. In accordance with an embodiment of the present invention, a method for processing control comprises diagnosing a chamber of a processing tool that processes a wafer to identify a key chamber parameter, and controlling the chamber based on the key chamber parameter if the key chamber parameter can be controlled, or compensating a prediction model by changing to a secondary prediction model if the key chamber parameter cannot be sufficiently controlled. | 01-13-2011 |
20110060441 | Clustering for Prediction Models in Process Control and for Optimal Dispatching - A first embodiment is a method for semiconductor process control comprising clustering processing tools of a processing stage into a tool cluster based on processing data and forming a prediction model for processing a semiconductor wafer based on the tool cluster. A second embodiment is a method for semiconductor process control comprising providing cluster routes between first stage tool clusters and second stage tool clusters, assigning a comparative optimization ranking to each cluster route, and scheduling processing of wafers. The comparative optimization ranking identifies comparatively which cluster routes provide for high wafer processing uniformity. Further, wafers that require high wafer processing uniformity are scheduled to be processed along one cluster route that has a high comparative optimization ranking that identifies the one cluster route to have a highest wafer processing uniformity, and wafers that do not require high wafer processing uniformity are scheduled to be processed along another cluster route. | 03-10-2011 |
20110126397 | PVD TARGET WITH END OF SERVICE LIFE DETECTION CAPABILITY - A PVD target structure for use in physical vapor deposition. The PVD target structure includes a consumable slab of source material and one or more detectors for indicating when the slab of source material is approaching or has been reduced to a given quantity representing a service lifetime endpoint of the target structure. Each detector includes an enclosure which may be made by forming a plurality of bores in a bulk material and separating the bulk material into a plurality of discrete enclosure units each including one of the bores. Alternatively, the enclosure of the detector may be made using a mold having one or more mold members and an extrusion, casting, electrical chemical plating, and/or sheet forming method. | 06-02-2011 |
20120131784 | PVD TARGET WITH END OF SERVICE LIFE DETECTION CAPABILITY - A method for forming a tube-based detector for signaling when a PVD target is reduced to a predetermined quantity of the PVD target material includes providing a mold member having an inner molding member and an outer molding member defining a space therebetween, melting a desired tube material, injecting the molten tube material into the space between the inner molding member and the outer molding member, cooling the molten tube material, removing the tube from the mold member after the molten tube material has cooled and solidified into a tube, embedding the tube in the physical vapor deposition target, wherein the tube forms an enclosure of the tube-based detector. | 05-31-2012 |
20130157412 | CHIP ON WAFER BONDER - The present disclosure provides a bonding apparatus. The bonding apparatus includes a cleaning module designed for cleaning chips; and a chip-to-wafer bonding chamber configured to receive the chips from the cleaning module and designed for bonding the chips to a wafer. | 06-20-2013 |