Jayasimha
Doddabaliapur Narasimha-Murthy Jayasimha, Sunnyvale, CA US
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20090265472 | Method, System, and Apparatus for System Level Initialization - Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. | 10-22-2009 |
Doddaballapur Jayasimha, Sunnyvale, CA US
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20130304957 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 11-14-2013 |
Doddaballapur N. Jayasimha, Sunnyvale, CA US
Patent application number | Description | Published |
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20090274157 | METHOD AND APPARATUS FOR HIERARCHICAL ROUTING IN MULTIPROCESSOR MESH-BASED SYSTEMS - A method and apparatus for hierarchical routing in mesh systems. The method may include splitting | 11-05-2009 |
20110213949 | METHODS AND APPARATUS FOR OPTIMIZING CONCURRENCY IN MULTIPLE CORE SYSTEMS - Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. Tag logic may be located within the interconnect, such as located in an agent, and configured to assign different interconnect tag identification numbers to two or more transactions from a same thread. The tag logic assigns different interconnect tag identification numbers to allow the two or more transactions from the same thread to be outstanding over the interconnect to two or more different target IP cores at the same time, allow the two or more transactions from the same thread to be processed in parallel over the interconnect, and potentially serviced out of issue order while being returned back to the multiple threaded initiator IP core realigned in expected execution order. | 09-01-2011 |
20130051397 | CREDIT FLOW CONTROL SCHEME IN A ROUTER WITH FLEXIBLE LINK WIDTHS UTILIZING MINIMAL STORAGE - A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router. | 02-28-2013 |
20130073878 | APPARATUS AND METHODS FOR AN INTERCONNECT POWER MANAGER - An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is partitioned into multiple power domains and has hardware circuitry integrated into the IN to manage a quiescent state for all components in each power domain in the IN when a routing pathway for transactions in the IN spans across one or more power domain boundaries and causes interdependencies of power domains within the IN other than where the power domains of the initiator agent and final target agent of the transaction are located within. The SPM is configured to cooperate and communicate with the IPM to quiesce, to wake up, and any combination of the two, one or more of the multiple power domains within the IN. | 03-21-2013 |
20130318308 | SCALABLE CACHE COHERENCE FOR A NETWORK ON A CHIP - Maintaining cache coherence in a System-on-a-Chip with both multiple cache coherent master IP cores (CCMs) and non-cache coherent master IP cores (NCMs). A plug-in cache coherence manager (CM), coherence logic in agents, and an interconnect are used for the SoC to provide a scalable cache coherence scheme that scales to an amount of CCMs in the SoC. The CCMs each includes at least one processor operatively coupled through the CM to at least one cache that stores data for that CCM. The CM maintains cache coherence responsive to a cache miss of a cache line on a first cache of the caches, then broadcasts a request for an instance of the data stored corresponding to cache miss of the cache line in the first cache. Each CCM maintains its own coherent cache and each NCM is configured to issue communication transactions into both coherent and non-coherent address spaces. | 11-28-2013 |
20140314076 | CREDIT FLOW CONTROL SCHEME IN A ROUTER WITH FLEXIBLE LINK WIDTHS UTILIZING MINIMAL STORAGE - A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router. | 10-23-2014 |
Jay Jayasimha, Sunnyvale, CA US
Patent application number | Description | Published |
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20090024715 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 01-22-2009 |
20090055600 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 02-26-2009 |
Sriram Jayasimha, Hyderabad IN
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20110028086 | SYSTEM AND METHOD FOR ENABLING ULTRA SMALL APERTURE COMMUNICATION ANTENNA USING SPECTRAL REPLICATION AND COHERENT FREQUENCY AND PHASE COMBINING - A satellite communications system has a hub terminal which communicates with a remote terminal through a satellite. The hub terminal | 02-03-2011 |
20110028087 | SYSTEM AND METHOD FOR ENABLING ULTRA SMALL APERTURE COMMUNICATION ANTENNA USING SPECTRAL REPLICATION AND COHERENT FREQUENCY AND PHASE COMBINING - A system for enabling use of ultra-small aperture terminals in satellite communications is provided. The system comprises a transmitter configured to receive an input signal having information, a bandwidth, and an amplitude, replicate the input signal into two or more replications of the input signal, convert each of the two or more replications to have a frequency tuned to two or more corresponding satellite transponders while maintaining the bandwidth and all the information of the input signal, and combine the two or more replications into a single uplink signal. A transmit antenna is configured to transmit the uplink signal to the two or more satellite transponders. | 02-03-2011 |
20110028088 | SYSTEM AND METHOD FOR ENABLING ULTRA SMALL APERTURE COMMUNICATION ANTENNA USING SPECTRAL REPLICATION AND COHERENT FREQUENCY AND PHASE COMBINING - A system for enabling use of ultra-small aperture terminals in satellite communications is provided. The system comprises a transmitter configured to receive an input signal having information, a bandwidth, and an amplitude, replicate the input signal into two or more replications of the input signal, convert each of the two or more replications to have a frequency tuned to two or more corresponding satellite transponders while maintaining the bandwidth and all the information of the input signal, and combine the two or more replications into a single uplink signal. A transmit antenna is configured to transmit the uplink signal to the two or more satellite transponders. | 02-03-2011 |
20110275326 | SHORT-PERIODICITY CARRIER ACQUISITION FOR SATCOM INTERFERENCE CANCELLATION - A technique for interference cancellation in a satellite communication system involves an autocorrelation on the hub signal to detect a periodicity in the hub signal, determining a search range for a delay in the hub echo signal in accordance with the periodicity, locating the delay in the hub echo signal, and performing the interference cancellation in accordance with the delay. In the case of periodicity, a delay is acquired (either true or false) that provides cancellation (provided that the period does not change). When the period changes, cancellation is discovered to be poor, and another delay (that may be true or false) is acquired that provides good cancellation and so on. | 11-10-2011 |
Sriram Jayasimha, Bangalore IN
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20120100800 | AUTOMATIC UPLINK POWER CONTROL IN INTERFERENCE CANCELLATION BASED SPECTRAL REUSE - A system and method for performing automatic uplink power control (AUPC), using interference cancellation, to compensate for signal attenuation in a satellite communication system in which uplink path attenuation, forward channel attenuation, or both are estimated at a hub station without requiring signal quality reports from a remote station, and without requiring a satellite beacon. Estimates of uplink path attenuation or forward channel attenuation are used by the hub station to control the output power of a transmitted signal, thereby compensating for the estimated attenuation. | 04-26-2012 |
20140273815 | POWER BOOSTER IN AN MEO SETTING - A customer satellite terminal provides seamless hand-off from a descending satellite to an ascending satellite in an equatorial MEO constellation at RF. The hand-off from the descending satellite to the ascending satellite is conducted when the propagation delay from the ascending satellite and the descending satellite are equal, by aligning first and second amplitudes, first and second frequency offsets, and first and second phases. | 09-18-2014 |
Varsha Jayasimha, Redmond, WA US
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20100325159 | MODEL-BASED IMPLIED AUTHORIZATION - An authorization system determines a user's permission to access an object implicitly based on relationships in a data-driven model. The system provides the ability to mark a relationship type in the model between one object class (accessor) and another object class (accessed) as an implicit authorization relationship type. A user can define the permissions granted to the accessor object on the accessed object. When an accessor object tries to access a related accessed object over an authorization relationship type, the authorization system determines the permissions granted by inspecting the implicit authorization relationship type definition. The authorization system can also traverse containment relationship types to grant objects permissions contained by other objects. The authorization system dynamically determines authorization based on a relationship model that more naturally fits the actions that an administrator of a data-driven system is familiar with, and does not involve complex direct authorization or group membership management. | 12-23-2010 |