Jayakumar
John V. Jayakumar, Chennai IN
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20150281395 | PROVIDING CONTENT BASED ON USER BANDWIDTH - A system may be configured to store different versions of a particular item of content, according to a group of content templates; and select a particular content template, of the group of content templates, to use in providing content in response to a request received from a user device. The particular content template may be selected based on bandwidth information regarding the user device. The bandwidth information may indicate a level of service to which a subscriber, associated with the user device, has subscribed. The bandwidth information may be based on a signal strength to a user device in a particular location. | 10-01-2015 |
Lenard John Stephan Jayakumar, Bangalore IN
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20110280125 | Adaptive Queue-Management - In one embodiment, a method includes storing in a QoS-enabled communication system a data structure that has a multi-level hierarchy including a physical level, a logical level, and a class level; receiving a first request for M number of services provided by the QoS-enabled communication system; in response to the first request, modifying an allocation of the logical-level nodes by mapping M class-level nodes to a first one of the logical-level nodes according to a first mapping mode of the data structure; receiving a second request for P services provided by the QoS-enabled communication system, with P being greater than M; and, in response to the second request, modifying an allocation of the logical-level nodes by mapping P class-level nodes to a second one of the logical-level nodes according to a second mapping mode of the data structure. | 11-17-2011 |
Lenard John Stephan Jayakumar, Wellesley, MA US
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20130094358 | ADAPTIVE QUEUE-MANAGEMENT - In one embodiment, a method includes storing in a QoS-enabled communication system a data structure that has a multi-level hierarchy including a physical level, a logical level, and a class level; receiving a first request for M number of services provided by the QoS-enabled communication system; in response to the first request, modifying an allocation of the logical-level nodes by mapping M class-level nodes to a first one of the logical-level nodes according to a first mapping mode of the data structure; receiving a second request for P services provided by the QoS-enabled communication system, with P being greater than M; and, in response to the second request, modifying an allocation of the logical-level nodes by mapping P class-level nodes to a second one of the logical-level nodes according to a second mapping mode of the data structure. | 04-18-2013 |
Marathurai S. Jayakumar, Lexington, MA US
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20120186477 | ENHANCED RELIABILITY MINIATURE PISTON ACTUATOR FOR AN ELECTRONIC THERMAL BATTERY INITIATOR - A system for a piston actuator comprising a configuration with lead styphnate charge material and Nichrome® bridgewire, wherein the device configuration provides very high reliability, including piston actuator applications; resistance of the bridgewire is carefully controlled to optimize power transfer from the firing circuit to the bridgewire and charge material. | 07-26-2012 |
Murali Jayakumar, Charlotte, NC US
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20150278774 | TECHNIQUES FOR HASH INDEXING - Apparatus for hash indexing is provided. The apparatus may be used to process a database operation request. The request may relate to a database element. The requested database element may correspond to an alphanumeric ABA routing identifier and a bank account identifier. The method may include receiving the operation request, performing a hashing operation on each of the alphanumeric ABA routing identifier and the bank account identifier to form a key for use with the operation request and performing the operation request using the key to obtain an output string. While rendering a result of the operation request for display, the method may further include comparing or filtering the output string to determine whether the output string correctly corresponds to the ABA routing identifier and a bank account identifier. The method may also include, following the comparing or filtering, displaying the output string. | 10-01-2015 |
Pon Samuel Jayakumar, Camel, IN US
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20130035233 | NOVEL HERBICIDE RESISTANCE GENES - The subject invention provides novel plants that are not only resistant to 2,4-D, but also to pyridyloxyacetate herbicides. Heretofore, there was no expectation or suggestion that a plant with both of these advantageous properties could be produced by the introduction of a single gene. The subject invention also includes plants that produce one or more enzymes of the subject invention “stacked” together with one or more other herbicide resistance genes. The subject invention enables novel combinations of herbicides to be used in new ways. Furthermore, the subject invention provides novel methods of preventing the development of, and controlling, strains of weeds that are resistant to one or more herbicides such as glyphosate. The preferred enzyme and gene for use according to the subject invention are referred to herein as AAD-12 (AryloxyAlkanoate Dioxygenase). This highly novel discovery is the basis of significant herbicide tolerant crop trait and selectable marker opportunities. | 02-07-2013 |
Pon Samuel Jayakumar, Carmel, IN US
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20150080218 | NOVEL HERBICIDE RESISTANCE GENES - The subject invention provides novel plants that are not only resistant to 2,4-D, but also to pyridyloxyacetate herbicides. Heretofore, there was no expectation or suggestion that a plant with both of these advantageous properties could be produced by the introduction of a single gene. The subject invention also includes plants that produce one or more enzymes of the subject invention “stacked” together with one or more other herbicide resistance genes. The subject invention enables novel combinations of herbicides to be used in new ways. Furthermore, the subject invention provides novel methods of preventing the development of, and controlling, strains of weeds that are resistant to one or more herbicides such as glyphosate. The preferred enzyme and gene for use according to the subject invention are referred to herein as AAD-12 (AryloxyAlkanoate Dioxygenase). This highly novel discovery is the basis of significant herbicide tolerant crop trait and selectable marker opportunities. | 03-19-2015 |
Prabhu Jayakumar, Chennai IN
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20160092810 | MULTI-DIMENSIONAL TARGET SETTING APPLICATION - Systems, methods, and non-transitory computer-readable mediums having program instructions thereon, provide for creating, storing and utilizing planned target data with a target-setting graphical user application based a cloud-based system. The target-setting application can create multi-dimensional target settings for any HANA or non-HANA based data source. The target-setting application can store planned targets for entities of an organization across varying dimensions and time granularity. Also, the target-setting application generates data access protocol service links of the target data so the target data can be consumed by both HANA and non-HANA based applications. | 03-31-2016 |
20160110670 | RELATIONAL ANALYSIS OF BUSINESS OBJECTS - Systems, methods, and non-transitory computer-readable mediums having program instructions thereon, provide for analyzing a business object corresponding to a data source with a relational analysis graphical user interface application. The relational analysis graphical user interface application facilitates the analysis of business objects corresponding to a data source through an interactive graphical path. The interactive graphical path depicts a suggested analysis path relating to the business object (i.e., entity). The suggested analysis path corresponds to any relationships (direct or indirect) between the selected entity and other related entities (i.e., corresponding to other data sources). Further, the relationship between the entities is determined based on a heuristic logic. | 04-21-2016 |
P. Samuel Jayakumar, Carmel, IN US
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20100159598 | In Vitro Methods for the Induction and Maintenance of Plant Cell Lines as Single Suspension Cells With Intact Cell Walls, and Transformation Thereof - The subject invention provides simple and consistent methods to break suspension cell aggregates to single cells with intact primary cell walls. The subject invention relates in part to cell separation of suspension cell aggregates cultured in medium containing pectin-degrading enzymes or tubulin de-polymerizing compounds including colchicine. The subject invention also relates to novel uses of compounds for such purposes. Another aspect of the subject invention relates to transformation of the subject, isolated cells. Such processes simplify and integrate single-cell-based transformation and selection processes into transgenic and transplastomic event-generation work processes. The subject invention also removes technical constraints and produces marker-free and uniformly expressing transgenic lines in a high throughput fashion to support various needs of animal health, biopharma, and trait and crop protection platforms. | 06-24-2010 |
20120034697 | IN VITRO METHODS FOR THE INDUCTION AND MAINTENANCE OF PLANT CELL LINES AS SINGLE SUSPENSION CELLS WITH INTACT CELL WALLS, AND TRANSFORMATION THEREOF - The subject invention provides simple and consistent methods to break suspension cell aggregates to single cells with intact primary cell walls. The subject invention relates in part to cell separation of suspension cell aggregates cultured in medium containing pectin-degrading enzymes or tubulin de-polymerizing compounds including colchicine. The subject invention also relates to novel uses of compounds for such purposes. Another aspect of the subject invention relates to transformation of the subject, isolated cells. Such processes simplify and integrate single-cell-based transformation and selection processes into transgenic and transplastomic event-generation work processes. The subject invention also removes technical constraints and produces marker-free and uniformly expressing transgenic lines in a high throughput fashion to support various needs of animal health, biopharma, and trait and crop protection platforms. | 02-09-2012 |
Sarathy Jayakumar, Portland, OR US
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20080288815 | Firmware assisted error handling scheme - A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system. | 11-20-2008 |
20090172372 | METHODS AND APPARATUS FOR GENERATING SYSTEM MANAGEMENT INTERRUPTS - A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed. | 07-02-2009 |
20100332707 | Bi-directional handshake for advanced reliabilty availability and serviceability - In some embodiments a signal is sent from a Basic Input/Output System to a device to indicate that the Basic Input/Output System needs to obtain control of shared resources. A signal is sent from the device to the Basic Input/Output System that indicates that the Basic Input/Output System can now control the shared resources. Other embodiments are described and claimed. | 12-30-2010 |
20110154104 | Controlling Memory Redundancy In A System - In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed. | 06-23-2011 |
20110179311 | INJECTING ERROR AND/OR MIGRATING MEMORY IN A COMPUTING SYSTEM - In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed. | 07-21-2011 |
20120079306 | Memory Reconfiguration During System Run-Time - Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device. | 03-29-2012 |
20130151569 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 06-13-2013 |
20130212426 | Controlling Memory Redundancy In A System - In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed. | 08-15-2013 |
20130254602 | FIRMWARE ASSISTED ERROR HANDLING SCHEME - A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system. | 09-26-2013 |
20130332781 | RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS - Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor. | 12-12-2013 |
20140053024 | COMPUTING PLATFORM WITH INTERFACE BASED ERROR INJECTION - In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, hardware component error injection. | 02-20-2014 |
20140059368 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 02-27-2014 |
20140188829 | TECHNOLOGIES FOR PROVIDING DEFERRED ERROR RECORDS TO AN ERROR HANDLER - Technologies to generate an error record are described herein. A method includes performing a scan of one or more error logs to identify a source of data in response to an attempt to access the data, determining whether an amount of time to complete the scan will exceed a threshold value, and generating a notice that the error record will be deferred based on the determination. A system includes a data collector to scan one or more error logs to identify a source of data in response to an attempt to access the data, a controller to determine whether an amount of time to scan the error logs to identify the source of data will exceed a threshold value, and a signal generator to generate a signal indicating that the error record is to be deferred based on the determination. | 07-03-2014 |
20140258701 | COMPUTING PLATFORM PERFORMANCE MANAGEMENT WITH RAS SERVICES - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface. | 09-11-2014 |
20140281092 | SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS - Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed. | 09-18-2014 |
20150089287 | EVENT-TRIGGERED STORAGE OF DATA TO NON-VOLATILE MEMORY - An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system. | 03-26-2015 |
20150161037 | FAST CACHE FLUSH - Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in a volatile memory, determine whether the first data element is to be stored in a nonvolatile memory, and in response to a determination that the first data element is to be stored in a nonvolatile memory, to forward the first transaction to the memory controller coupled to the nonvolatile memory. Other examples are also disclosed and claimed. | 06-11-2015 |
20150186278 | RUNTIME PERSISTENCE - Apparatus, systems, and methods to manage memory operations are described. In one embodiment, a controller is coupled to a processor unit, and comprising logic to block additional transactions on the processor unit, initiate a cache flush to flush data from cache memory coupled to the processor unit to a memory controller buffer, block incoming data from the cache memory, and initiate a buffer flush to flush data from the memory controller buffer to a nonvolatile memory. Other examples are also disclosed and claimed. | 07-02-2015 |
20150378841 | Techniques to Communicate with a Controller for a Non-Volatile Dual In-Line Memory Module - Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some examples, selective assertion of bits maintained in registers accessible through the SMBus interface may enable communication with the controller. The selective assertion may be based on a register map. | 12-31-2015 |
Shalini Jayakumar, Tamil Nadu IN
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20150293049 | Sensing Device and Method of Fabricating the Same - The present invention provides a sensing device. The sensing device at least comprises a substrate, a layer of gold material and a layer of diamond nanowires, in which the layer of gold material is disposed on the substrate and the layer of diamond nanowires is disposed on the layer of gold material. A method of fabricating the abovementioned sensing device is also disclosed in the present invention. | 10-15-2015 |
Suchithra Jayakumar, Bentonville, AR US
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20140201747 | CROSS PLATFORM WORKFLOW MANAGEMENT - A method and system for real-time monitoring of processes to obtain job data of jobs running on different non-compatible platforms with a Java monitoring agent, then saving, reporting and making the job data available at any time for viewing by a system administrator on a single display monitor. | 07-17-2014 |