Patent application number | Description | Published |
20090321788 | DIELECTRIC LEDGE FOR HIGH FREQUENCY DEVICES - High frequency performance of (e.g., silicon) bipolar devices ( | 12-31-2009 |
20090321879 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices ( | 12-31-2009 |
20100013051 | Method Of Forming A Bipolar Transistor And Semiconductor Component Thereof - A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer. | 01-21-2010 |
20100059860 | COUNTER-DOPED VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 03-11-2010 |
20100314664 | SILICIDED BASE STRUCTURE FOR HIGH FREQUENCY TRANSISTORS - High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. Emitter, base and collector regions are formed in or on a semiconductor substrate. The emitter contact has a portion that overhangs a portion of the extrinsic base contact, thereby forming a cave-like cavity between the overhanging portion of the emitter contact and the underlying regions of the extrinsic base contact. When the emitter contact and the extrinsic base contact are silicided, some of the metal atoms forming the silicide penetrate into the cavity so that the highly conductive silicided extrinsic base contact extends under the edge of the emitter contact closer to the base itself, thereby reducing Rbx. Smaller Rbx provides transistors with higher f | 12-16-2010 |
20110215411 | Method for Forming an Independent Bottom Gate Connection For Buried Interconnection Including Bottom Gate of a Planar Double Gate MOSFET - A method is provided for making a semiconductor device, which comprises (a) providing a semiconductor structure comprising a top gate ( | 09-08-2011 |
20120080804 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME - A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity. | 04-05-2012 |
20120199881 | BIPOLAR TRANSISTOR AND METHOD WITH RECESSED BASE ELECTRODE - High frequency performance of (e.g., silicon) bipolar devices ( | 08-09-2012 |
20130266042 | TEMPERATURE SENSOR - A temperature sensor includes a constant current source and a transistor stack connected to the constant current source. The transistor stack includes a first transistor having a base connected to the constant current source and a collector coupled to a supply voltage. The collector of the first transistor is electrically isolated from the base of the first transistor. The transistor stack includes a second transistor connected to the first transistor. The second transistor has a collector connected to an emitter of the first transistor and has a base connected to the collector of the second transistor. The transistor stack includes an output node disposed between the constant current source and the base of the first transistor. A voltage of the output node is indicative of a temperature. | 10-10-2013 |
20140001650 | ELECTRONIC DEVICE INCLUDING INTERCONNECTS WITH A CAVITY THEREBETWEEN AND A PROCESS OF FORMING THE SAME | 01-02-2014 |
20140131772 | SEMICONDUCTOR DEVICES WITH RECESSED BASE ELECTRODE - High frequency performance of (e.g., silicon) bipolar devices is improved by reducing the extrinsic base resistance Rbx. An emitter, an intrinsic base, and a collector are formed in a semiconductor body. An emitter contact has a region that overlaps a portion of an extrinsic base contact. A sidewall is formed in the extrinsic base contact proximate a lateral edge of the overlap region of the emitter contact. The sidewall is amorphized during or after formation so that when the emitter contact and the extrinsic base contact are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall so that part of the highly conductive silicided extrinsic base contact extends under the edge of the overlap region of the emitter contact closer to the intrinsic base, thereby reducing Rbx. Smaller Rbx provides transistors with higher f | 05-15-2014 |
20140147985 | METHODS FOR THE FABRICATION OF SEMICONDUCTOR DEVICES INCLUDING SUB-ISOLATION BURIED LAYERS - Methods for fabricating a semiconductor device are provided. In one embodiment, the method includes forming a Sub-Isolation Buried Layer (SIBL) stack over a semiconductor substrate. The SIBL stack includes a polish stop layer and a sacrificial implant block layer. The SIBL stack is patterned to create an opening therein, and the semiconductor substrate is etched through the opening to produce a trench in the semiconductor substrate. Ions are implanted into the semiconductor substrate at a predetermined energy level at which ion penetration through the patterned SIBL stack is substantially prevented to create a SIBL region beneath the trench. After ion implantation, a trench fill material is deposited over the SIBL stack and into the trench. The semiconductor device is polished to remove a portion of the trench fill material along with the sacrificial implant block layer and expose the polish stop layer. | 05-29-2014 |