Patent application number | Description | Published |
20120248614 | METHODS FOR FORMING A SEMICONDUCTOR STRUCTURE AND RELATED STRUCTURES - Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the dielectric material to expose the bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 μm. Semiconductor structures formed by such methods are also disclosed. | 10-04-2012 |
20130175698 | Integrated Circuit Constructions Having Through Substrate Vias And Methods Of Forming Integrated Circuit Constructions Having Through Substrate Vias - An integrated circuit construction includes a stack of two or more integrated circuit substrates. At least one of the substrates includes through substrate vias (TSVs) individually comprising opposing ends. A conductive bond pad is adjacent one of the ends on one side of the one substrate. A conductive solder mass is adjacent the other end projecting elevationally on the other side of the one substrate. Individual of the solder masses are bonded to a respective bond pad on an immediately adjacent substrate of the stack. Epoxy flux surrounds the individual solder masses. An epoxy material different in composition from the epoxy flux surrounds the epoxy flux on the individual solder masses. Methods of forming integrated circuit constructions are also disclosed. | 07-11-2013 |
20130234319 | SEMICONDUCTOR CONSTRUCTIONS - Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts. | 09-12-2013 |
20130240939 | SOLID STATE LIGHTING DEVICES HAVING SIDE REFLECTIVITY AND ASSOCIATED METHODS OF MANUFACTURE - Solid state lighting devices having side reflectivity and associated methods of manufacturing are disclosed herein. In one embodiment, a method of forming a solid state lighting device includes attaching a solid state emitter to a support substrate, mounting the solid state emitter and support substrate to a temporary carrier, and cutting kerfs through the solid state emitter and the substrate to separate individual dies. The solid state emitter can have a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The individual dies can have sidewalls that expose the first semiconductor material, active region and second semiconductor material. The method can further include applying a reflective material into the kerfs and along the sidewalls of the individual dies. | 09-19-2013 |
20130299965 | SEMICONDUCTOR ASSEMBLIES, STRUCTURES, AND METHODS OF FABRICATION - Semiconductor assemblies, structures, and methods of fabrication are disclosed. A coating is formed on an electrically conductive pillar. The coating, which may be formed from at least one of a silane material and an organic solderability protectant material, may bond to a conductive material of the electrically conductive pillar and, optionally, to other metallic materials of the electrically conductive pillar. The coating may also bond to substrate passivation material, if present, or to otherwise-exposed surfaces of a substrate and a bond pad. The coating may be selectively formed on the conductive material. Material may not be removed from the coating after formation thereof and before reflow of the solder for die attach. The coating may isolate at least the conductive material from solder, inhibiting solder wicking or slumping along the conductive material and may enhance adhesion between the resulting bonded conductive element and an underfill material. | 11-14-2013 |
20130299986 | METHODS FOR FORMING SEMICONDUCTOR DEVICE PACKAGES WITH PHOTOIMAGEABLE DIELECTRIC ADHESIVE MATERIAL, AND RELATED SEMICONDUCTOR DEVICE PACKAGES - Methods for forming semiconductor device packages include applying a photoimageable dielectric adhesive material to a major surface of a semiconductor die and at least partially over conductive elements on the semiconductor die. The photoimageable dielectric adhesive material may be removed from over the conductive elements. The conductive elements are aligned with and bonded to bond pads of a substrate, and the semiconductor die and the substrate are adhered with the photoimageable dielectric adhesive material. A semiconductor device package includes at least one semiconductor die including conductive structures thereon, a substrate including bond pads thereon that are physically and electrically connected to the conductive structures, and a developed photoimageable dielectric adhesive material disposed between the semiconductor die and the substrate around and between adjacent conductive structures. | 11-14-2013 |
20130309861 | Semiconductor Constructions and Methods of Planarizing Across a Plurality of Electrically Conductive Posts - Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts. | 11-21-2013 |
20130313710 | Semiconductor Constructions and Methods of Forming Semiconductor Constructions - Some embodiments include semiconductor constructions. The constructions have an electrically conductive post extending through a semiconductor die. The post has an upper surface above a backside surface of the die, and has a sidewall surface extending between the backside surface and the upper surface. A photosensitive material is over the backside surface and along the sidewall surface. Electrically conductive material is directly against the upper surface of the post. The electrically conductive material is configured as a cap over the post. The cap has an edge that extends laterally outwardly beyond the post and encircles the post. An entirety of the edge is directly over the photosensitive material. Some embodiments include methods of forming semiconductor constructions having photosensitive material adjacent through-wafer interconnects, and having electrically conductive material caps over and directly against upper surfaces of the interconnects and directly against an upper surface of the photosensitive material. | 11-28-2013 |
20140042618 | METHODS FOR FORMING A SEMICONDUCTOR STRUCTURE AND RELATED STRUCTURES - Methods of forming a Ni material on a bond pad are disclosed. The methods include forming a dielectric material over a bond pad, forming an opening within the dielectric material to expose the bond pad, curing the dielectric material to form a surface of the dielectric material having a steep curvilinear profile, and forming a nickel material over the at least one bond pad. The dielectric material having a steep curvilinear profile may be formed by altering at least one of a curing process of the dielectric material and a thickness of the dielectric material. The dielectric material may be used to form a relatively thick Ni material on bond pads smaller than about 50 μm. Semiconductor structures formed by such methods are also disclosed. | 02-13-2014 |
20140070832 | INTERCONNECT ASSEMBLIES WITH PROBED BOND PADS - An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad. | 03-13-2014 |
20140159239 | METHODS OF SELECTIVELY REMOVING A SUBSTRATE MATERIAL AND RELATED SEMICONDUCTOR STRUCTURES - A method for selective removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The method comprises oxidizing a semiconductor structure comprising a substrate and at least one copper feature and removing a portion of the substrate using an etchant comprising SF | 06-12-2014 |
20140291834 | SEMICONDUCTOR DEVICES AND PACKAGES INCLUDING CONDUCTIVE UNDERFILL MATERIAL AND RELATED METHODS - Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate. | 10-02-2014 |
20150035126 | METHODS AND STRUCTURES FOR PROCESSING SEMICONDUCTOR DEVICES - Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at least adjacent a periphery of the carrier substrate, adhesively bonding another substrate to the carrier substrate, and separating the another substrate from the carrier substrate. The silane material includes a compound having a structure of (XO) | 02-05-2015 |