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Jason Brown
Jason Brown, Round Rock, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20100041438 | Multiple Subscription Subscriber Identity Module (SIM) Card - Embodiments of the invention include a multiple subscription subscriber identity module (SIM) card. The SIM card includes a plurality of sets of subscription parameters from which to select and activate a single set of parameters. The sets of subscription parameters each contain various information, e.g., information such as an Integrated Circuit Card Identifier (ICCID) and an International Mobile Subscriber Identity (IMSI), and are based on various criteria, e.g., different service regions of use for the electronic device on which the SIM card is installed. A set of subscription parameters is selected for a particular region of use either manually or automatically. The SIM card, which can include a software interface that provides a list of available sets of subscription parameters, is activated by updating the selected set of subscription parameters. Alternatively, a default set of subscription parameters is selected unless a different set of subscription parameters is selected manually from among the plurality of sets of subscription parameters. According to alternative embodiments of the invention, the selected set of subscription parameters can be deactivated and a different set of subscription parameters can be selected and updated to in the SIM card. | 02-18-2010 |
| 20110077051 | UICC Control Over Devices Used to Obtain Service - Devices and methods are disclosed by which a smart card or UICC that is removably insertable into a wireless terminal will only allow operation in either a specific terminal or a specific set of terminals. A mechanism to restrict the set of terminals that a UICC will operate with based upon logic embedded in a memory within the UICC. The UICC receives specific information from the wireless terminal when the terminal is turned on. If the information received satisfies a plurality of rules or conditions stored within the UICC, the UICC functions normally and the terminal may be registered with the network. If the UICC is inserted in an unsupported terminal, the UICC will refuse to function normally. This provides a deterrent against UICC theft. | 03-31-2011 |
Jason Brown, Locksbottom Kent GB
| Patent application number | Description | Published |
|---|---|---|
| 20110050418 | SECURITY SYSTEM - A security system comprising: a controller; and a plurality of dispensing devices, wherein the controller is configured to receive signals from a plurality of remote detectors and transmit signals to the plurality of dispensing devices, the controller being adapted to determine which of the plurality of detectors has transmitted a signal and transmit a signal to a selected one or more dispensing devices to dispense a fluid based on said determination, wherein each dispensing device is configured to receive signals from the controller and dispense fluid when a signal is received. | 03-03-2011 |
Jason Brown, Greenville, RI US
| Patent application number | Description | Published |
|---|---|---|
| 20110015002 | SPORTS PRACTICE REBOUND NET - An adjustable sports practice net provides a ball rebounding flat net or nearly flat net target area surrounded by a large rebound net area. Target poles and a target net may simulate a full size sports net. End posts are sunk into the ground or attached to external vertical structures. Flexibility in setting up the sports practice net enables it to fit within a given space available. The target area is adjustable to position in alignment with outside end posts or positioned at a range of distances set back from the end posts to tighten the net between the target frame and the outside end posts and frame. Various rebound angles may be set up. | 01-20-2011 |
Jason Brown, Allen, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20090108871 | METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER - Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up transistor, a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor, a primary pull-down pre-driver operably coupled to a primary pull-down transistor, and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. Each of the primary pull-up pre-driver, the secondary pull-up pre-driver., primary pull-down pre-driver, and the secondary pull-down pre-driver are configured to provide a voltage to a gate of a transistor operably coupled thereto at a voltage level so as to sustain gate dielectric integrity of the transistor. | 04-30-2009 |
| 20100026344 | METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER - Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices. | 02-04-2010 |
| 20100054058 | SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY - Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address. | 03-04-2010 |
| 20100208533 | SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY - Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked loop may be used to compensate for additional delay experienced by the system clock relative to write clock and ensure synchronization of the clock signals. A write latch enable block may be used to develop a write latch enable signal for issuance along with a corresponding address signal. The write latch enable signal can be timed such that it arrives at an appropriate time to issue the data corresponding to the issued address. | 08-19-2010 |
| 20100254198 | WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME - Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. The FF circuit latches the internal write command in response to an internal write command FF signal based on a write clock signal and generates an internal write enable signal in response to latching the internal write command. The write data register captures write data in response to the write clock signal and releases the captured write data in response to a delayed internal write enable signal. | 10-07-2010 |
Jason Brown, Philadelphia, PA US
Jason Brown, San Luis Obispo, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090187481 | AUTOMATIC GENERATION OF ELECTRONIC ADVERTISING MESSAGES - A facility for generating an advertising message is described. The facility extracts visual content from a model web page. The facility then constructs an advertising message that contains the extracted visual content. | 07-23-2009 |
Jason Brown, Frisco, TX US
| Patent application number | Description | Published |
|---|---|---|
| 20080307479 | Bandwidth-Efficient Deployment of Video-On-Demand Assets in an IPTV Network - An IPTV network and a method are described herein that seamlessly integrate a multicast-based file transfer mechanism with unicast IPTV middleware to enable the efficient transfer of VOD assets from a Super Headend Office (SHO) to one or more Video Hub Offices (VHOs). | 12-11-2008 |